Winbond Electronics Corporation W25Q128JWBIQ TR
- Part No.:
- W25Q128JWBIQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128JWBIQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q128JWBIQ TR from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with up to 133MHz clock frequency, 4KB uniform sector architecture, and industrial temperature range (–40°C to +105°C). It enables XIP execution, code shadowing, and secure firmware storage in space-constrained embedded systems.
For engineers reviewing the W25Q128JWBIQ TR datasheet, W25Q128JWBIQ TR pinout, W25Q128JWBIQ TR application, or W25Q128JWBIQ TR equivalent, key selection criteria include Quad I/O timing compliance, /WP and /HOLD functional mapping per package, 1.8V VCC tolerance, sector-level write protection granularity, and reset behavior across SOIC/WSON/TFBGA variants.
Technical Context
The W25Q128JWBIQ TR implements a flexible SPI interface with three operational modes: Standard (DI/DO), Dual (IO0/IO1), and Quad (IO0–IO3), where Quad mode requires non-volatile QE bit (Status Register-2, bit 1) to be set. Its 65,536 × 256-byte pages support 1–256 byte page programming and erase operations at 4KB/32KB/64KB granularity.
It integrates volatile and non-volatile status register bits for block protection (BP2–BP0), top/bottom selection (TB), security lock (LB3–LB1), and output driver strength (DRV1/DRV0), alongside hardware /WP and /HOLD pins active-low, with /RESET available only on SOIC-16 and TFBGA packages - not on the WSON 8-pin variant of W25Q128JWBIQ TR.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB) organized as 65,536 × 256-byte pages |
| Supply Voltage | 1.7–1.95 V - strict 1.8V operation; incompatible with 3.3V SPI buses without level shifting |
| Max Clock Frequency | 133 MHz for Quad I/O - enables 532 Mbps effective throughput using Fast Read Quad I/O (EBh) |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (256), and 64 KB blocks (128) |
| Endurance & Retention | 100,000 program/erase cycles minimum; >20 years data retention at 85°C |
| Operating Temperature | –40°C to +105°C - qualified for Industrial Plus grade applications |
| Security Features | 64-bit unique ID, SFDP register, 3×256-byte OTP-lockable security registers, individual sector lock (36h/39h) |
Pinout & Package
W25Q128JWBIQ TR uses an 8-pin WSON 6×5-mm package (Package Code P), with no dedicated /RESET pin. Pin functions are shared across SPI modes: /CS selects device, CLK clocks transfers, DI/DO serve as IO0/IO1 in Standard/Dual mode, /WP becomes IO2 and /HOLD becomes IO3 in Quad mode when QE=1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO and standby current when high |
| 2 DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad modes |
| 3 /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware write lock for status register; becomes IO2 in Quad mode when QE=1 |
| 4 GND | Ground Reference | Primary return path for VCC and I/O signals; must be low-impedance |
| 5 DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad modes |
| 6 CLK | Serial Clock Input | Edge-triggered timing source; supports SPI Mode 0 and Mode 3 |
| 7 /HOLD (IO3) | Hold Input / Bidirectional I/O | Pauses ongoing read/write; becomes IO3 in Quad mode when QE=1; no /RESET function |
| 8 VCC | Power Supply | 1.7–1.95 V supply; internal regulation ensures stable core voltage |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O Interface | Enables 532 Mbps effective bandwidth via Fast Read Quad I/O (EBh), eliminating need for parallel NOR in bandwidth-sensitive boot code fetch |
| Erase/Program Suspend | Allows background read access during long erase/program cycles (75h/7Ah), improving real-time system responsiveness |
| Volatile & Non-Volatile Protection | Combines hardware /WP pin with BP/TB/SEC/CMP bits and OTP security registers to enforce multi-layer firmware integrity |
| Uniform 4KB Sector Architecture | Supports fine-grained parameter storage and over-the-air (OTA) update partitioning without wasted space from larger erase blocks |
| Industrial Plus Grade | Qualified for –40°C to +105°C operation with full spec compliance, enabling use in automotive under-hood and industrial motor control |
Applications
| Secure Firmware Storage | Boot Code Execution (XIP) |
|---|---|
|
Use Scenario: Storing signed bootloader images and cryptographic keys in edge IoT gateways requiring tamper-resistant storage. IC Role / Device Role / Timing Role: Non-volatile code and configuration store with hardware write protection and OTP-locked security registers. Use Value: Prevents unauthorized firmware modification via dual-layer protection: /WP pin + non-volatile BP/TB bits + LB1–LB3 OTP locks. |
Use Scenario: Directly executing application firmware from flash in resource-limited microcontrollers (e.g., ARM Cortex-M0+) without RAM copy. IC Role / Device Role / Timing Role: High-speed Quad SPI memory providing deterministic instruction fetch latency via Fast Read Quad I/O (EBh). Use Value: Achieves 66 MB/s continuous read throughput - sufficient for real-time audio decoding and sensor fusion algorithms. |
| Industrial OTA Updates | Parameter & Calibration Data Logging |
|
Use Scenario: Field-upgradable firmware in programmable logic controllers (PLCs) where partial reflash must avoid erasing critical runtime parameters. IC Role / Device Role / Timing Role: Sector-erasable storage enabling atomic swap between active/inactive firmware partitions. Use Value: 4KB uniform sectors allow independent erase of firmware image sections without disturbing calibration tables or network credentials. |
Use Scenario: Recording sensor calibration coefficients and runtime diagnostics in factory automation HMIs operating at extended temperature. IC Role / Device Role / Timing Role: Reliable, low-power non-volatile storage with >20-year data retention at 105°C ambient. Use Value: Eliminates need for external EEPROM or battery-backed SRAM by guaranteeing data integrity across thermal cycling and power loss events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q128JVSIM TR | 3.3V supply (2.7–3.6V), same density and Quad SPI capability, but lacks Industrial Plus temperature rating (only –40°C to +85°C) | Suitable for commercial-grade consumer electronics; not rated for 105°C operation | Select W25Q128JVSIM TR only if system VCC is 3.3V and ambient temperature stays ≤85°C. |
| Micron MT25QL128ABA8ESF-0SIT | 1.8V supply, same 128M-bit density and Quad SPI, but uses different status register layout and lacks /HOLD pin functionality in Quad mode | Requires firmware adaptation for status bit interpretation and hold/resume sequence handling | Choose MT25QL128ABA8ESF-0SIT only when cross-platform firmware abstraction layers already handle vendor-specific register maps. |
Compared with W25Q128JWBIQ TR, W25Q128JVSIM TR trades industrial temperature range for 3.3V compatibility, while MT25QL128ABA8ESF-0SIT offers identical voltage but demands register-level firmware changes - making W25Q128JWBIQ TR optimal for new 1.8V designs needing guaranteed 105°C operation and minimal driver porting.
Availability
W25Q128JWBIQ TR is available at Aetrix Electronics and suitable for industrial motor drives, automotive ADAS modules, and medical diagnostic equipment requiring stable component supply across extended temperature and long product lifecycles.
Supply support for W25Q128JWBIQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including NOR/NAND flash and SRAM, with global manufacturing and quality certifications.
The W25Q series targets high-reliability embedded systems demanding fast, secure, and low-voltage serial flash - designed specifically for code execution, firmware storage, and parameter logging in industrial, automotive, and networking applications.
FAQ
What is the supply voltage range for W25Q128JWBIQ TR, and is it compatible with 3.3V systems?
W25Q128JWBIQ TR operates strictly within 1.7–1.95 V and is not 3.3V-tolerant. Connecting it directly to a 3.3V SPI bus will damage the device. Level-shifting circuitry is mandatory for interfacing with 3.3V microcontrollers. The W25Q128JWBIQ TR datasheet explicitly prohibits exceeding 2.0 V on any pin, including I/Os, under any condition.
Does W25Q128JWBIQ TR include a hardware /RESET pin, and how is it accessed?
No, W25Q128JWBIQ TR does not include a hardware /RESET pin. That function is only available on SOIC-16 (Package Code F) and TFBGA (Package Codes B/C) variants - not on the WSON 6×5-mm package used by W25Q128JWBIQ TR. Reset must be performed via software sequence: Enable Reset (66h) followed by Reset (99h), which takes ~30 µs.
How does Quad SPI mode activate on W25Q128JWBIQ TR, and what pin changes occur?
Quad SPI mode activates when the Quad Enable (QE) bit in Status Register-2 (bit 1) is set to '1'. Once enabled, the /WP pin becomes IO2 and the /HOLD pin becomes IO3. This remapping is non-volatile if written to the non-volatile portion of the register. The W25Q128JWBIQ TR must be configured for Quad mode before issuing Quad I/O instructions like EBh (Fast Read Quad I/O).
What is the smallest erasable unit on W25Q128JWBIQ TR, and why does it matter for firmware updates?
The smallest erasable unit on W25Q128JWBIQ TR is a 4KB sector - there are 4,096 such sectors. This granularity enables precise firmware partitioning: one sector for bootloader, others for application images and rollback slots. Unlike larger-block flashes, it avoids erasing unrelated data during partial updates, preserving calibration values and device identity across W25Q128JWBIQ TR field upgrades.
Can W25Q128JWBIQ TR's /WP pin provide hardware write protection for both status registers and memory array?
The /WP pin on W25Q128JWBIQ TR protects only the status registers (SRP/SRL bits) - not the main memory array. Full memory protection requires configuring non-volatile block protect (BP2–BP0), top/bottom (TB), and complement (CMP) bits in the status register, optionally combined with individual sector locks (36h/39h). /WP alone cannot prevent accidental writes to user data sectors.
W25Q128JWBIQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- -, 3ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128JWBIQ TR FAQ
1.How can I place an order for W25Q128JWBIQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JWBIQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JWBIQ TR reliable?
The price and inventory of W25Q128JWBIQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWBIQ TR is usually 5 days.
3.What payment methods are accepted for W25Q128JWBIQ TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWBIQ TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JWBIQ TR?
W25Q128JWBIQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JWBIQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JWBIQ TR?
For technical support, including W25Q128JWBIQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWBIQ TR requirements.
6.How does Aetrix verify that W25Q128JWBIQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JWBIQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWBIQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128JWBIQ TR?
All W25Q128JWBIQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWBIQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JWBIQ TR part is unused and in its original packaging.
Return procedure for W25Q128JWBIQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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