Winbond Electronics Corporation W25Q128JWCIQ TR
- Part No.:
- W25Q128JWCIQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128JWCIQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,176
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128JWCIQ TR from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory supporting Standard, Dual, and Quad SPI interfaces with up to 133MHz clock frequency, 532MHz equivalent Quad I/O throughput, and 4KB uniform sector architecture - used for code execution (XIP), firmware storage, and parameter retention in space-constrained industrial embedded systems.
For engineers reviewing the W25Q128JWCIQ TR datasheet, W25Q128JWCIQ TR pinout, W25Q128JWCIQ TR application, or W25Q128JWCIQ TR equivalent, key selection considerations include Quad Enable (QE) bit configuration, /HOLD vs /RESET pin availability per package, 1.7–1.95V supply compliance, hardware write protection via /WP, and sector-level erase flexibility for firmware update partitioning.
Technical Context
The W25Q128JWCIQ TR implements a quad-I/O SPI interface requiring non-volatile QE bit (Status Register-2, Bit 1) to be set for IO2 (/WP) and IO3 (/HOLD) activation. It supports SPI modes 0 and 3, with dual/quad instructions enabling burst reads at up to 66MB/s continuous transfer rate using Fast Read Quad I/O (EBh).
Its flexible erase hierarchy includes 4KB sectors (4,096 total), 32KB blocks (2,048), and 64KB blocks (1,024), plus chip erase. Erase/program suspend/resume functionality enables concurrent background operations, while 64-bit unique ID and SFDP register support standardized parameter discovery and secure device identification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB) - supports full firmware images for mid-tier microcontrollers without external memory expansion. |
| Supply Voltage | 1.7 V to 1.95 V - compatible with low-voltage industrial SoCs and battery-backed systems; no level-shifting required. |
| Quad SPI Clock Rate | Up to 133 MHz - enables 532 Mbps effective bandwidth (133 MHz × 4 lines), exceeding parallel NOR performance in pin-constrained designs. |
| Erase Granularity | Uniform 4 KB sectors - allows fine-grained firmware update partitioning and robust OTA rollback without erasing entire application space. |
| Endurance & Retention | 100,000 program/erase cycles; >20-year data retention - validated for long-life industrial deployments with frequent field updates. |
| Operating Temperature | −40°C to +105°C - qualified for extended industrial and automotive under-hood applications per Industrial Plus Grade spec. |
| Security Features | OTP-locked security registers (3×256 bytes), individual sector lock/unlock (36h/39h), and 64-bit unique ID - enables secure boot key storage and anti-cloning. |
Pinout & Package
W25Q128JWCIQ TR is supplied in an 8-pin WSON 6×5-mm package (Package Code P), with exposed pad for thermal dissipation. Pin 1 is /CS; pins 2–3 and 5 are bidirectional I/Os (IO1, IO2, IO0); pin 4 is GND; pin 6 is CLK; pin 7 is /HOLD (functions as IO3 in Quad mode); pin 8 is VCC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable: drives DO/IOx high-Z when deasserted; required to transition H→L before instruction acceptance post-power-up. |
| DO / IO1 (Pin 2) | Data Output / Quad I/O Line 1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad modes - carries read data or address bits depending on instruction phase. |
| /WP / IO2 (Pin 3) | Write Protect Input / Quad I/O Line 2 | Hardware write lock for status register when low; becomes IO2 in Quad mode only after QE=1 is set in Status Register-2. |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and I/O signals; requires low-impedance connection to system ground plane for signal integrity. |
| DI / IO0 (Pin 5) | Data Input / Quad I/O Line 0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad modes - carries instructions, addresses, and write data on CLK rising edge. |
| CLK (Pin 6) | Serial Clock Input | Synchronizes all SPI transfers; supports Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1); max 133 MHz in Quad I/O. |
| /HOLD / IO3 (Pin 7) | Hold Input / Quad I/O Line 3 | Pauses ongoing read/write when low (active); repurposed as IO3 in Quad mode only when QE=1 - not available if /RESET is needed. |
| VCC (Pin 8) | Power Supply | 1.7–1.95 V nominal; internal LDO regulates core logic; <1 µA typical power-down current reduces standby power in always-on systems. |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O Interface with QE Control | Enables 4-line bidirectional data transfer at 133 MHz; QE bit must be set non-volatily to activate IO2/IO3 - critical for XIP latency optimization. |
| Erase/Program Suspend & Resume | Allows interrupting a sector erase or page program to service a higher-priority read request, then resuming - essential for real-time firmware update coexistence. |
| Individual Sector Lock (36h/39h) | Permits locking/unlocking of any 4KB sector via dedicated instructions - enables secure bootloader partitioning independent of BP bits. |
| Discoverable Parameters (SFDP) | Standardized JEDEC SFDP register (5Ah) provides programmable timing, voltage, and feature parameters - eliminates hard-coded driver assumptions. |
| 64-Bit Unique Device ID | Factory-programmed read-only identifier (4Bh) - supports device authentication, secure provisioning, and traceability in production and field service. |
| Industrial Plus Grade Temp Range | Rated −40°C to +105°C with full electrical specs guaranteed - suitable for motor control, PLC, and transportation electronics without derating. |
Applications
| Firmware Storage in Edge AI Nodes | Secure Bootloader Partitioning |
|---|---|
|
Use Scenario: Storing inference model binaries and runtime configuration in compact edge AI gateways with limited PCB area and no parallel bus. IC Role / Device Role / Timing Role: Primary non-volatile code storage with Quad SPI XIP capability, delivering 66 MB/s sustained read throughput to feed Cortex-M7/M33 caches. Use Value: Eliminates need for external RAM loading; 4KB sector granularity enables atomic over-the-air updates of model weights without disrupting active inference. |
Use Scenario: Isolating immutable bootloader code from updatable application firmware in industrial controllers subject to IEC 62443 security requirements. IC Role / Device Role / Timing Role: Secure firmware vault with OTP-locked security registers and individual sector lock (36h) protecting first 128KB of flash. Use Value: Prevents unauthorized modification of boot code via hardware-enforced write protection and cryptographic key storage in locked security registers. |
| Parameter Storage in Motor Drives | Code Shadowing in PLC CPUs |
|
Use Scenario: Retaining calibration coefficients, fault logs, and tuning parameters across power cycles in servo drive modules operating at 105°C ambient. IC Role / Device Role / Timing Role: High-reliability parameter store with >20-year data retention and 100K endurance - accessed via Fast Read (0Bh) during startup initialization. Use Value: Guarantees parameter persistence under thermal stress; 4KB sectors allow independent erase of logs without affecting calibration data. |
Use Scenario: Loading ladder logic runtime images into SRAM at power-on for deterministic scan-cycle execution in modular PLC backplanes. IC Role / Device Role / Timing Role: High-speed code shadowing source using Fast Read Quad I/O (EBh) at 133 MHz to achieve sub-100ms boot time. Use Value: Reduces boot latency by 4× vs standard SPI; uniform sector layout simplifies image alignment and avoids partial-sector read penalties. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 3V supply (2.7–3.6V); no /HOLD pin in 8-pin SOIC; lacks SFDP register and OTP security registers. | Requires level-shifting for 1.8V systems; no standardized parameter discovery; reduced security for bootloader use cases. | Select only if legacy 3V design compatibility is mandatory and security features are unnecessary. |
| S25FL128SAGMFI000 | 1.8V operation; includes HyperBus interface option; larger 16-pin SOIC package; supports execute-in-place with tighter tVSL timing. | Better suited for high-performance MCU co-processors needing deterministic XIP latency; less optimal for ultra-compact WSON layouts. | Prefer when HyperBus bandwidth or guaranteed XIP timing margins outweigh footprint constraints. |
Compared with MX25L12833FZC-10G, W25Q128JWCIQ TR delivers lower-voltage operation, richer security, and standardized SFDP - making it superior for new 1.8V industrial designs. Against S25FL128SAGMFI000, W25Q128JWCIQ TR offers smaller WSON packaging and broader SPI mode support but lacks HyperBus - favoring cost-sensitive, space-constrained applications over peak XIP performance.
Availability
W25Q128JWCIQ TR is available at Aetrix Electronics and suitable for industrial automation, edge AI inference nodes, and motor control systems requiring stable component supply, long-term lifecycle assurance, and guaranteed Industrial Plus temperature grade compliance.
Supply support for W25Q128JWCIQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based global semiconductor manufacturer specializing in specialty memory solutions, including serial NOR/NAND flash, RAM, and mobile DRAM - serving industrial, automotive, and communications markets since 1987.
The W25Q series was designed specifically for high-reliability embedded systems demanding fast, secure, and low-voltage serial flash - emphasizing Quad SPI performance, sector-level flexibility, and industrial-grade endurance and temperature resilience.
FAQ
What is the function of the /HOLD pin on W25Q128JWCIQ TR, and how does it behave in Quad SPI mode?
The /HOLD pin on W25Q128JWCIQ TR pauses ongoing SPI operations when pulled low while /CS is active, placing DO/IOx in high-impedance state. In Quad SPI mode, this pin functions as IO3 - but only after the Quad Enable (QE) bit in Status Register-2 is set to '1'. When QE=0, /HOLD remains active; when QE=1, /HOLD is repurposed and cannot perform hold functionality. This behavior is strictly defined in the W25Q128JWCIQ TR datasheet Section 4.4 and Figure 1a.
Does W25Q128JWCIQ TR support hardware reset, and which packages include the dedicated /RESET pin?
W25Q128JWCIQ TR supports both software reset (66h + 99h sequence) and hardware reset. However, the dedicated /RESET pin is **not present** in the WSON 6×5-mm (P-code) package of W25Q128JWCIQ TR. It is only available in SOIC-16 (F-code) and TFBGA-24 (B/C-code) variants. The W25Q128JWCIQ TR uses /HOLD (Pin 7) as its sole control pin for hold/reset multiplexing - confirming no hardware reset capability in this specific variant.
How is Quad SPI mode enabled on W25Q128JWCIQ TR, and what happens to the /WP and /HOLD pins?
Quad SPI mode on W25Q128JWCIQ TR is enabled by setting the Quad Enable (QE) bit - Bit 1 of Status Register-2 - to '1' via Write Status Register-2 (31h) instruction. Once QE=1, the /WP pin (Pin 3) becomes IO2 and the /HOLD pin (Pin 7) becomes IO3. Both pins lose their hardware protection and hold functions permanently until QE is cleared - a change that persists across power cycles unless explicitly reconfigured. This mapping is fixed per W25Q128JWCIQ TR's pin description in Section 3.3.
What is the minimum and maximum supply voltage for reliable operation of W25Q128JWCIQ TR?
W25Q128JWCIQ TR operates reliably within a supply voltage range of 1.7 V to 1.95 V, as specified in Section 9.2 (Operating Ranges) of its datasheet. Operation below 1.7 V may cause undefined behavior or failure to accept commands; above 1.95 V risks permanent damage. The device includes internal voltage monitoring - automatic reset occurs if VCC drops below threshold during operation - ensuring data integrity in brown-out conditions relevant to W25Q128JWCIQ TR deployments.
Can W25Q128JWCIQ TR be used for Execute-in-Place (XIP), and what interface mode is recommended?
Yes, W25Q128JWCIQ TR supports Execute-in-Place (XIP) directly from flash memory. For optimal XIP performance, Quad SPI mode using Fast Read Quad I/O (EBh) instruction is recommended - delivering up to 66 MB/s continuous read throughput at 133 MHz clock. This eliminates bottlenecks seen with Standard or Dual SPI, and is validated for use with ARM Cortex-M and RISC-V cores requiring low-latency instruction fetch - a key capability confirmed for W25Q128JWCIQ TR in Section 1 General Descriptions.
W25Q128JWCIQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128JWCIQ TR FAQ
1.How can I place an order for W25Q128JWCIQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JWCIQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JWCIQ TR reliable?
The price and inventory of W25Q128JWCIQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWCIQ TR is usually 5 days.
3.What payment methods are accepted for W25Q128JWCIQ TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWCIQ TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JWCIQ TR?
W25Q128JWCIQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JWCIQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JWCIQ TR?
For technical support, including W25Q128JWCIQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWCIQ TR requirements.
6.How does Aetrix verify that W25Q128JWCIQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JWCIQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWCIQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128JWCIQ TR?
All W25Q128JWCIQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWCIQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JWCIQ TR part is unused and in its original packaging.
Return procedure for W25Q128JWCIQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JWCIQ TR Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

