My Inquiry
My Account
Winbond Electronics Corporation W25Q128JWEIM TR
- Part No.:
- W25Q128JWEIM TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128JWEIM TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:
- Shipping:
Inventory:4,937
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128JWEIM TR from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory supporting Standard, Dual, and Quad SPI interfaces with up to 133MHz clock frequency and 532MHz equivalent Quad I/O throughput. It features uniform 4KB sectors, 100K program-erase cycles, and 20-year data retention. Designed for code execution (XIP), firmware storage, and parameter logging in space-constrained industrial systems.
For engineers reviewing the W25Q128JWEIM TR datasheet, W25Q128JWEIM TR pinout, W25Q128JWEIM TR application, or W25Q128JWEIM TR equivalent, this device delivers high-speed Quad I/O performance, hardware write protection via /WP and /HOLD pins, flexible sector/block erase granularity, and industrial-grade temperature operation (−40°C to +105°C).
Technical Context
The W25Q128JWEIM TR implements a quad-I/O SPI interface requiring the non-volatile Quad Enable (QE) bit in Status Register-2 to be set; when enabled, /WP becomes IO2 and /HOLD becomes IO3. It supports SPI modes 0 and 3, with configurable output driver strength (DRV1/DRV0) and erase/program suspend/resume functionality.
Its architecture includes 65,536 pages of 256 bytes each, organized into 4,096 erasable 4KB sectors and 256 erasable 64KB blocks. Security features include 64-bit unique ID, SFDP register, three 256-byte OTP-lockable security registers, and individual sector/block lock/unlock instructions (36h/39h/3Dh).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB) - supports full firmware images and boot code in compact embedded designs. |
| Supply Voltage | 1.7–1.95 V - enables direct integration with 1.8V logic domains without level shifting. |
| Quad SPI Clock Rate | Up to 133 MHz - enables 532 MB/s effective throughput using Fast Read Quad I/O (EBh) instruction. |
| Erase Granularity | 4 KB sectors, 32 KB & 64 KB blocks - allows fine-grained firmware updates and parameter storage without full chip erase. |
| Endurance & Retention | 100,000 program-erase cycles; >20 years data retention - suitable for field-upgradable industrial controllers. |
| Operating Temperature | −40°C to +105°C - qualified for industrial-plus grade applications including motor drives and power converters. |
| Write Protection | Hardware (/WP pin), software (BPx/TB/SEC/CMP bits), and OTP-locked security registers - multi-layer defense against accidental corruption. |
Pinout & Package
W25Q128JWEIM TR uses an 8-pad WSON 6×5-mm package (Package Code P), with wettable flank profile for automated optical inspection. Pin 1 is /CS; pins 2–3–5–7 are bidirectional I/Os (IO1, IO2, IO0, IO3); pin 4 is GND; pin 6 is CLK; pin 8 is VCC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable: asserts device selection and transitions from standby to active current (~1 mA). |
| 2 DO (IO1) | Data Output / I/O1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad mode - used for read data and address transmission. |
| 3 /WP (IO2) | Write Protect Input / I/O2 | Active-low hardware lock for status register; repurposed as IO2 when Quad Enable (QE=1) is set. |
| 4 GND | Ground Reference | Primary return path for VCC and I/O signals; requires low-impedance PCB connection to minimize noise coupling. |
| 5 DI (IO0) | Data Input / I/O0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad mode - carries instructions, addresses, and write data. |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference (up to 133 MHz); must meet setup/hold requirements per AC specs (tSU, tH). |
| 7 /HOLD (IO3) | Hold Input / I/O3 | Pauses ongoing SPI transfer when low; repurposed as IO3 in Quad mode; not available if QE=1. |
| 8 VCC | Power Supply | 1.7–1.95 V supply; decoupling capacitor (≥1 µF X7R) required within 5 mm of pin for stable read/write margins. |
Key Features
| Feature | Design Value |
|---|---|
| Quad I/O Interface | Enables 4-line data transfer (IO0–IO3) at 133 MHz, delivering 532 MB/s effective bandwidth - eliminates need for parallel NOR in cost-sensitive XIP designs. |
| Erase/Program Suspend | Supports 75h/7Ah instructions to pause and resume erase/program operations - critical for real-time systems requiring deterministic latency. |
| Individual Sector Lock | 36h/39h/3Dh instructions allow per-sector (4KB) read/write lock/unlock - enables secure bootloader partitioning and OTA update staging. |
| 64-Bit Unique ID | Factory-programmed immutable identifier accessible via 4Bh instruction - enables device authentication and secure provisioning in IIoT edge nodes. |
| SFDP Register | Standard Flash Discovery Parameter support (5Ah) - allows automatic configuration of timing, voltage, and feature sets by host bootloader without hard-coded tables. |
Applications
| Industrial Motor Control | Medical Diagnostic Imaging |
|---|---|
|
Use Scenario: Storing calibrated sensor coefficients, motor profile tables, and safety-critical firmware patches in servo drives operating at −40°C to +105°C. IC Role / Device Role / Timing Role: Non-volatile firmware and parameter storage with XIP-capable Quad SPI interface enabling deterministic boot and runtime code fetch. Use Value: 4KB sector erase allows over-the-air updates to motion control algorithms without disrupting active motor operation or safety monitoring routines. |
Use Scenario: Holding DICOM metadata templates, image calibration LUTs, and regulatory-compliant boot firmware in portable ultrasound units. IC Role / Device Role / Timing Role: High-reliability code and data storage with OTP-protected security registers for HIPAA-compliant device identity and audit logs. Use Value: 100K endurance and 20-year retention ensure consistent image fidelity and traceability across 10+ year product lifecycles without field recalibration. |
| Smart Grid IoT Gateway | Automotive ADAS Camera Module |
|
Use Scenario: Hosting encrypted firmware images, TLS root certificates, and time-synchronized event logs in DIN-rail-mounted grid edge controllers. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage with hardware /WP pin and SFDP-driven configuration for interoperable firmware upgrades. Use Value: Dual/Quad SPI flexibility allows seamless migration from legacy SPI hosts to higher-bandwidth SoCs without PCB redesign. |
Use Scenario: Storing camera calibration parameters, ISP firmware, and ASIL-B compliant boot code in compact rear-view and surround-view modules. IC Role / Device Role / Timing Role: Industrial-grade flash memory with −40°C to +105°C operation and 64-bit unique ID for ECU-level traceability. Use Value: Uniform 4KB sectors enable atomic firmware updates during vehicle ignition cycles, meeting ISO 26262 functional safety requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12835FZC-10G | 3V supply (2.7–3.6V); no /HOLD pin in 8-pin SOIC; lacks OTP security registers and SFDP support. | Requires level-shifting for 1.8V systems; limited security capability for secure boot implementations. | Select only if existing 3V infrastructure prohibits voltage rail redesign and security requirements are minimal. |
| S25FL128SAGMFI001 | 1.8V supply; supports HyperBus interface (not SPI); 16-pin SOIC or BGA packages only; no WSON 6×5-mm option. | Higher bandwidth (up to 333 MHz DDR) but incompatible pinout and protocol - mandates full PCB and firmware rework. | Choose only when HyperBus host controller is already deployed and maximum sequential read speed is prioritized over footprint and SPI compatibility. |
Compared with MX25L12835FZC-10G and S25FL128SAGMFI001, the W25Q128JWEIM TR uniquely combines 1.8V operation, WSON 6×5-mm packaging, Quad SPI performance, OTP security registers, and SFDP configurability - making it optimal for new industrial and medical designs where size, voltage compatibility, and security are co-prioritized.
Availability
W25Q128JWEIM TR is available at Aetrix Electronics and suitable for industrial motor control, medical imaging devices, smart grid gateways, and automotive ADAS camera modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for W25Q128JWEIM TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for industrial, communications, and consumer markets.
The W25Q series is engineered for high-performance, low-voltage embedded systems requiring reliable code storage, XIP execution, and robust data integrity - targeting industrial automation, medical electronics, and automotive infotainment.
FAQ
What is the package type and lead count of the W25Q128JWEIM TR?
The W25Q128JWEIM TR uses an 8-pad WSON (6 mm × 5 mm) package with wettable flanks. It has no leads - the pads are surface-mount terminals designed for reflow soldering. This compact footprint supports high-density PCB layouts in space-constrained industrial and medical applications, and the wettable flank geometry enables automated optical inspection of solder joints.
Does the W25Q128JWEIM TR support hardware reset via a dedicated /RESET pin?
No - the W25Q128JWEIM TR does not include a dedicated /RESET pin. That function is only available on SOIC-16 (Package Code F) and TFBGA (Package Codes B/C) variants. The W25Q128JWEIM TR relies on software reset (66h + 99h instructions) and power-cycle recovery. Its /HOLD pin (Pin 7) serves dual roles but cannot substitute for hardware reset.
How is Quad SPI mode enabled on the W25Q128JWEIM TR?
Quad SPI mode is enabled by setting the Quad Enable (QE) bit in Status Register-2 (SR2) using the Write Status Register-2 (31h) instruction. Once QE = 1, pins /WP (Pin 3) and /HOLD (Pin 7) become IO2 and IO3 respectively. The device then accepts Quad I/O instructions like Fast Read Quad I/O (EBh). QE can be configured as volatile or non-volatile depending on SR2's SRP1 bit setting.
What is the minimum erase block size supported by the W25Q128JWEIM TR?
The minimum erase block size is 4 KB - corresponding to one uniform sector. The W25Q128JWEIM TR supports sector erase (20h), 32 KB block erase (52h), 64 KB block erase (D8h), and full chip erase (C7h/60h). This 4 KB granularity enables precise firmware patching and parameter updates without disturbing adjacent code or data regions.
Can the W25Q128JWEIM TR be used in systems requiring secure boot verification?
Yes - the W25Q128JWEIM TR supports secure boot through multiple mechanisms: factory-programmed 64-bit unique ID (4Bh), three 256-byte OTP-lockable security registers (42h/44h/48h), and configurable status register protection (SRP/SRL bits). These features allow cryptographic key storage, device identity binding, and tamper-resistant boot image validation in certified industrial and medical platforms.
W25Q128JWEIM TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- -, 3ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (8x6)
W25Q128JWEIM TR FAQ
1.How can I place an order for W25Q128JWEIM TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JWEIM TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JWEIM TR reliable?
The price and inventory of W25Q128JWEIM TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWEIM TR is usually 5 days.
3.What payment methods are accepted for W25Q128JWEIM TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWEIM TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JWEIM TR?
W25Q128JWEIM TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JWEIM TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JWEIM TR?
For technical support, including W25Q128JWEIM TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWEIM TR requirements.
6.How does Aetrix verify that W25Q128JWEIM TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JWEIM TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWEIM TR meets industry standards.
7.What is the process for return or replacement of W25Q128JWEIM TR?
All W25Q128JWEIM TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWEIM TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JWEIM TR part is unused and in its original packaging.
Return procedure for W25Q128JWEIM TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JWEIM TR Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
