Winbond Electronics Corporation W25Q128JWEIQ TR
- Part No.:
- W25Q128JWEIQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128JWEIQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q128JWEIQ TR from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI interface, supporting up to 133MHz Quad I/O clocking and 66MB/s continuous read throughput. It features uniform 4KB sectors, hardware /WP and /HOLD pins, and operates across -40°C to +105°C for industrial-plus applications including boot code storage and XIP execution.
For engineers reviewing the W25Q128JWEIQ TR datasheet, W25Q128JWEIQ TR pinout, W25Q128JWEIQ TR application, or W25Q128JWEIQ TR equivalent, this page delivers verified package mapping (8-pad WSON 8x6-mm), confirmed Quad SPI timing behavior, JEDEC ID validation (EF4018), SFDP register support, and real-world erase/program cycle endurance (100K cycles).
Technical Context
The W25Q128JWEIQ TR implements a standard SPI bus with Mode 0 and Mode 3 compatibility, enabling seamless integration with ARM Cortex-M, RISC-V, and FPGA-based controllers. Its dual- and quad-I/O modes rely on configurable Status Register-2 bits - specifically the non-volatile Quad Enable (QE) bit - to repurpose /WP and /HOLD as IO2 and IO3.
It supports full instruction set compatibility with legacy W25Q128FV devices while adding enhanced security features: 64-bit unique ID, three 256-byte OTP-locked security registers, and individual sector/block lock/unlock commands (36h/39h/3Dh). Erase suspend/resume (75h/7Ah) enables concurrent background operations without halting host communication.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 1.7–1.95 V - enables direct interfacing with 1.8V logic families without level shifting |
| Quad SPI Clock Rate | Up to 133 MHz - delivers 532 Mbps effective bandwidth (133 MHz × 4 lines) |
| Read Throughput | 66 MB/s continuous - exceeds parallel NOR flash in bandwidth-per-pin efficiency |
| Erase Endurance | 100,000 program/erase cycles per sector - validated for firmware update partitions |
| Data Retention | 20+ years at +85°C - meets industrial lifecycle requirements for unattended systems |
| Operating Temp | -40°C to +105°C - qualified for under-hood automotive and industrial edge computing |
| JEDEC ID | EF4018 - enables automatic device detection and configuration in bootloader firmware |
Pinout & Package
W25Q128JWEIQ TR uses the 8-pad WSON 8x6-mm package (Package Code E), with wettable flank side walls for automated optical inspection (AOI) and improved solder joint reliability in reflow processes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO during deselect; must transition high→low after power-up before first instruction |
| 2 DO (IO1) | Data Output / Quad I/O Line 1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad mode; shares function with IO1 |
| 3 /WP (IO2) | Write Protect Input / Quad I/O Line 2 | Hardware write lock for status register when QE=0; becomes IO2 in Quad mode when QE=1 |
| 4 GND | Ground Reference | Primary return path for VCC and I/O signals; requires low-inductance PCB connection to minimize noise coupling |
| 5 DI (IO0) | Data Input / Quad I/O Line 0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad mode; shares function with IO0 |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference; supports Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1) |
| 7 /HOLD (IO3) | Hold Input / Quad I/O Line 3 | Pauses active transfers when low; disabled in Quad mode (reassigned to IO3); active-low with internal pull-up |
| 8 VCC | Power Supply | 1.7–1.95 V supply; decoupling capacitor (≥1 µF ceramic) required within 5 mm of pin for stable read/write margins |
Key Features
| Feature | Design Value |
|---|---|
| Quad Enable (QE) Bit | Non-volatile bit in Status Register-2 that permanently enables IO2/IO3 functionality - required for all Quad SPI instructions |
| Erase/Program Suspend | 75h/7Ah command pair allows pausing long erase or program operations to service urgent host reads without data loss |
| Individual Sector Lock | 36h/39h commands provide per-sector write protection independent of BP bits - ideal for secure parameter storage |
| Discoverable Parameters (SFDP) | 5Ah instruction returns standardized JEDEC SFDP v1.6 table - enables automatic driver configuration in Linux and RTOS BSPs |
| Unique 64-bit ID | 4Bh instruction retrieves factory-programmed immutable identifier - used for device authentication and firmware binding |
| Security Register OTP Lock | Three 256-byte regions (SR1–SR3) support one-time programming via 42h/44h/48h - prevents tampering with cryptographic keys |
Applications
| Boot Code Storage | Firmware Over-the-Air (OTA) |
|---|---|
|
Use Scenario: Storing primary bootloader and application firmware in embedded microcontrollers requiring cold-start execution. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Quad SPI interface enabling direct execution without RAM copy. Use Value: 133MHz Quad I/O reduces boot latency by >4× vs. standard SPI; 4KB sector granularity allows atomic firmware updates without erasing entire image. |
Use Scenario: Securely receiving and validating firmware patches in connected IoT gateways operating in remote locations. IC Role / Device Role / Timing Role: Trusted storage for signed firmware images with hardware write protection and OTP-secured key storage. Use Value: Individual sector lock (36h) isolates patch region; 64-bit UID binds firmware to device identity; SFDP auto-configures driver timing parameters. |
| Industrial HMI Display | Automotive ADAS Logging |
|
Use Scenario: Storing GUI assets, font tables, and localized language strings in human-machine interface panels deployed in factory environments. IC Role / Device Role / Timing Role: High-reliability data archive with 20-year retention and -40°C to +105°C operation. Use Value: Uniform 4KB sectors simplify asset versioning; /WP pin provides hardware-level protection against accidental UI corruption during field servicing. |
Use Scenario: Capturing sensor fusion logs and diagnostic snapshots in advanced driver-assistance systems with strict ASIL-B compliance requirements. IC Role / Device Role / Timing Role: Deterministic, low-latency logging buffer supporting concurrent read/write via erase suspend/resume. Use Value: 100K-cycle endurance ensures >10 years of daily log rotation; power-down current <1µA minimizes battery drain during vehicle sleep mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12835FZC-10G | 3V supply (2.7–3.6V), no /HOLD pin in 8-pin SOIC, lacks SFDP register and OTP security registers | Not suitable for 1.8V systems; cannot replace W25Q128JWEIQ TR without voltage translation and firmware revalidation | Select only if existing 3V design requires drop-in replacement with identical pinout and density |
| S25FL128SAGMFV010 | 1.8V operation, 128Mb density, but uses different command set (no 36h/39h sector lock), no unique ID, and slower 80MHz max Quad clock | Lacks per-sector locking and device identity - unsuitable for secure OTA or authenticated boot use cases | Consider for cost-sensitive industrial control where security and fine-grained protection are not required |
Compared with MX25L12835FZC-10G and S25FL128SAGMFV010, the W25Q128JWEIQ TR uniquely combines 1.8V operation, Quad SPI performance (133MHz), per-sector locking, 64-bit UID, and OTP-secured registers - making it the only option among the three qualified for secure, high-speed, industrial-plus boot and firmware storage.
Availability
W25Q128JWEIQ TR is available at Aetrix Electronics and suitable for industrial automation controllers, automotive telematics modules, and medical imaging subsystems requiring stable component supply, extended temperature qualification, and long-term obsolescence management.
Supply support for W25Q128JWEIQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash, RAM, and mobile DRAM, serving industrial, automotive, and communications markets since 1987.
The W25Q series was designed specifically for high-performance, low-voltage embedded systems requiring reliable code storage, fast XIP execution, and robust security - with the W25Q128JW family targeting industrial-plus and extended-temperature applications.
FAQ
What is the package type and footprint for W25Q128JWEIQ TR?
W25Q128JWEIQ TR uses the 8-pad WSON 8x6-mm package (Package Code E) with wettable flanks. Its footprint matches JEDEC MO-241AC, featuring 0.5mm pitch, exposed thermal pad, and side-wall solderability for automated optical inspection. This differs from the 208-mil SOIC or TFBGA variants in the same family.
Does W25Q128JWEIQ TR support hardware reset via /RESET pin?
No - W25Q128JWEIQ TR does not include a dedicated /RESET pin. That feature is only available on SOIC-16 (Package Code F) and TFBGA (Package Codes B/C) variants. The W25Q128JWEIQ TR relies solely on software reset (66h + 99h) and power-cycle recovery.
How is Quad SPI mode enabled on W25Q128JWEIQ TR?
Quad SPI mode is enabled by setting the Quad Enable (QE) bit in Status Register-2 using the Write Status Register-2 (31h) instruction. Once QE=1, pins /WP and /HOLD become IO2 and IO3 respectively. This change is non-volatile unless cleared, and must be verified via Read Status Register-2 (35h) before issuing Quad I/O commands like EBh.
What is the minimum /CS pulse width requirement after power-up for W25Q128JWEIQ TR?
After power-up, W25Q128JWEIQ TR requires /CS to transition from high to low before accepting any instruction. While no absolute minimum pulse width is specified, stable deassertion (>100 ns) followed by assertion is necessary to exit power-on reset state. A 1 µs /CS low pulse is recommended to ensure reliable initialization.
Can W25Q128JWEIQ TR be used in place of W25Q128FV without firmware changes?
W25Q128JWEIQ TR is backward-compatible with W25Q128FV for Standard and Dual SPI operations, but Quad SPI requires explicit QE bit configuration. Firmware must verify and set QE=1 before using Quad instructions. Also, W25Q128JWEIQ TR adds security register commands (42h/44h/48h) and enhanced protection bits not present in FV - unused features may be safely ignored.
W25Q128JWEIQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- -, 3ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (8x6)
W25Q128JWEIQ TR FAQ
1.How can I place an order for W25Q128JWEIQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JWEIQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JWEIQ TR reliable?
The price and inventory of W25Q128JWEIQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWEIQ TR is usually 5 days.
3.What payment methods are accepted for W25Q128JWEIQ TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWEIQ TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JWEIQ TR?
W25Q128JWEIQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JWEIQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JWEIQ TR?
For technical support, including W25Q128JWEIQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWEIQ TR requirements.
6.How does Aetrix verify that W25Q128JWEIQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JWEIQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWEIQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128JWEIQ TR?
All W25Q128JWEIQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWEIQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JWEIQ TR part is unused and in its original packaging.
Return procedure for W25Q128JWEIQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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