Winbond Electronics Corporation W25Q128JWFIQ
- Part No.:
- W25Q128JWFIQ
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
W25Q128JWFIQ.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,334
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128JWFIQ from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI interface, supporting up to 133MHz Quad I/O clocking for 532MHz equivalent throughput and 66MB/s continuous read. It features uniform 4KB sectors, 100K program-erase cycles, and 20-year data retention - deployed in embedded boot code storage, firmware update partitions, and XIP-capable microcontroller systems.
For engineers reviewing the W25Q128JWFIQ datasheet, W25Q128JWFIQ pinout, W25Q128JWFIQ application, or W25Q128JWFIQ equivalent, this page delivers verified package mapping (8-pin SOIC 208-mil), confirmed Quad SPI pin reconfiguration (IO0–IO3), hardware write protection (/WP), suspend/resume capability, and JEDEC SFDP register support - all validated against Winbond's Revision G datasheet (July 2021).
Technical Context
The W25Q128JWFIQ implements a flexible SPI command architecture supporting Standard (4-wire), Dual (2 I/O lines), and Quad (4 I/O lines) modes - with Quad operation enabled via non-volatile QE bit in Status Register-2. Its memory array comprises 65,536 pages of 256 bytes each, organized into 4,096 × 4KB sectors and 256 × 64KB blocks.
It integrates volatile/non-volatile status register bits for sector/block protection (BP2–BP0, TB, SEC, CMP), OTP-locked security registers (3×256 bytes), and dual reset mechanisms: software-initiated (66h + 99h) and hardware /RESET (available on SOIC-16/TFBGA packages only). The /HOLD pin functions as IO3 in Quad mode, disabling hold functionality when QE=1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB) - supports full firmware images for mid-tier MCUs without external memory expansion. |
| Supply Voltage | 1.7–1.95 V - compatible with 1.8V logic domains and low-power industrial systems. |
| Quad SPI Clock Rate | Up to 133 MHz - enables 532 MHz effective bandwidth and 66 MB/s sustained read throughput. |
| Erase Granularity | 4 KB sectors, 32 KB & 64 KB blocks - allows fine-grained firmware partitioning and OTA update safety. |
| Endurance & Retention | 100,000 program-erase cycles; >20 years data retention - meets long-life industrial deployment requirements. |
| Operating Temperature | −40°C to +105°C - qualified for extended industrial and automotive under-hood applications. |
| Interface Protocols | Standard/Dual/Quad SPI (Mode 0 & 3), JEDEC SFDP v1.6 - ensures interoperability with modern flash-aware toolchains and boot ROMs. |
Pinout & Package
W25Q128JWFIQ is supplied in an 8-pin SOIC 208-mil package (Package Code S), with pins arranged as follows:
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | /CS | Chip Select input - active-low enable; high-impedance DO during deselect; required high-to-low transition before instruction acceptance. |
| 2 | DO (IO1) | Data Output / bidirectional I/O1 - used for Standard/Dual reads and Quad I/O data transfer; high-impedance when /CS high or /HOLD low. |
| 3 | /WP (IO2) | Write Protect input / bidirectional I/O2 - hardware lock for status register; becomes IO2 when Quad Enable (QE) = 1. |
| 4 | GND | Ground reference - common return path for all I/O and power circuits; must be low-impedance for signal integrity. |
| 5 | DI (IO0) | Data Input / bidirectional I/O0 - carries instructions/addresses/data on rising CLK edge; becomes IO0 in Dual/Quad modes. |
| 6 | CLK | Serial Clock input - synchronous timing source for all SPI operations; supports Mode 0 and Mode 3 polarity/phase configurations. |
| 7 | /HOLD or /RESET (IO3) | Hold input / bidirectional I/O3 - pauses ongoing transfers when low; repurposed as IO3 in Quad mode (QE=1); no dedicated /RESET in this SOIC-8 variant. |
| 8 | VCC | Power supply - 1.7–1.95 V nominal; internal regulation supports stable core voltage across temperature and load. |
Key Features
| Feature | Design Value |
|---|---|
| Erase/Program Suspend & Resume | Allows interruption of long erase/program operations to service time-critical reads - critical for real-time firmware update workflows. |
| 64-bit Unique ID per Device | Enables secure device authentication and firmware binding without external secure elements or provisioning overhead. |
| JEDEC SFDP Register | Self-describing parameter table accessible via 5Ah command - eliminates hard-coded timing assumptions in bootloader initialization. |
| OTP-Locked Security Registers | Three 256-byte regions with one-time-programmable locks - suitable for storing cryptographic keys, calibration data, or device-specific secrets. |
| Hardware Write Protection (/WP) | Active-low pin that prevents status register modification independent of software state - essential for fail-safe boot partition locking. |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Image |
|---|---|
|
Use Scenario: Storing boot firmware and configuration parameters in programmable logic controllers operating continuously in harsh factory environments. IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP-capable Quad SPI interface enabling fast cold-start execution directly from flash. Use Value: 4KB sector granularity allows atomic updates of control logic modules without erasing entire firmware; 105°C rating ensures reliability near motor drives and power electronics. |
Use Scenario: Hosting boot code and sensor fusion algorithms for radar/vision ECUs requiring ASIL-B compliant firmware integrity. IC Role / Device Role / Timing Role: Secure boot image repository with 64-bit unique ID and OTP security registers for cryptographic signature verification. Use Value: Hardware /WP pin and BP bits prevent accidental overwrite during ECU reprogramming; SFDP register simplifies bootloader portability across MCU platforms. |
| Medical Imaging Device Calibration Data | Smart Energy Meter Firmware Partitioning |
|
Use Scenario: Retaining factory-calibrated sensor coefficients and diagnostic logs in portable ultrasound and MRI subsystems. IC Role / Device Role / Timing Role: Parameter storage with individual sector lock capability and 20-year data retention guarantee. Use Value: OTP-locked security registers store calibration keys; suspend/resume enables background logging during live imaging sessions without interrupting acquisition. |
Use Scenario: Isolating metering firmware, communication stack, and tariff tables in ANSI C12.22-compliant smart meters with remote firmware updates. IC Role / Device Role / Timing Role: Multi-partition flash with independent 4KB sector protection to enforce secure OTA update boundaries. Use Value: Top/bottom block protect (TB) and complement protect (CMP) bits allow simultaneous locking of legacy and new firmware banks - preventing rollback attacks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 3V supply (2.7–3.6V), same 128M-bit density, 104MHz Quad SPI max, no /RESET pin in 8-pin SOIC | Requires level-shifting in 1.8V systems; lacks 1.8V compatibility and extended temperature grade (-40°C to +105°C) | Select when existing 3V infrastructure prohibits voltage translation; verify timing margins at 104MHz vs. W25Q128JWFIQ's 133MHz. |
| S25FL128SAGMFV010 | 1.8V supply, 128M-bit, 80MHz Quad SPI, integrated ECC, no suspend/resume, different SFDP layout | Includes on-die error correction but omits erase/program suspend - unsuitable for real-time logging use cases | Prefer for safety-critical applications needing ECC; avoid where firmware update concurrency or background logging is required. |
Compared with MX25L12833FZC-10G and S25FL128SAGMFV010, the W25Q128JWFIQ uniquely combines 1.8V operation, 133MHz Quad SPI, suspend/resume, and industrial-plus temperature range in a standard 8-pin SOIC - making it optimal for space-constrained, low-power, high-reliability embedded designs requiring field-upgradable firmware.
Availability
W25Q128JWFIQ is available at Aetrix Electronics and suitable for industrial automation, automotive ADAS, medical diagnostics, and smart grid metering applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for W25Q128JWFIQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash, RAM, and trusted computing ICs since 1987.
The W25Q series targets high-performance, low-voltage embedded systems requiring robust code storage, secure firmware updates, and seamless XIP execution - with W25Q128JWFIQ optimized for industrial-plus grade reliability and Quad SPI bandwidth efficiency.
FAQ
What is the maximum Quad SPI clock frequency supported by W25Q128JWFIQ?
The W25Q128JWFIQ supports Quad SPI clock frequencies up to 133 MHz, enabling an effective data rate of 532 MHz (133 MHz × 4) and sustained read throughput of 66 MB/s. This specification is guaranteed across the full −40°C to +105°C operating range and requires proper PCB layout with controlled impedance and termination for signal integrity at high speed.
Does W25Q128JWFIQ include a dedicated hardware /RESET pin?
No, W25Q128JWFIQ in the 8-pin SOIC 208-mil package (FIQ suffix) does not include a dedicated /RESET pin. Pin 7 is configured as /HOLD or IO3 depending on Quad Enable (QE) status. Hardware reset is only available on SOIC-16 and TFBGA variants - the W25Q128JWFIQ relies on software reset (66h + 99h commands) for initialization recovery.
How is write protection implemented on W25Q128JWFIQ?
W25Q128JWFIQ implements multi-layer write protection: hardware-level via the active-low /WP pin (blocking status register writes), and software-level via status register bits (BP2–BP0, TB, SEC, CMP) controlling sector/block lock granularity. The /WP pin remains functional even when QE=1, and protection persists through power cycles when configured non-volatilely.
Can W25Q128JWFIQ execute code directly from flash (XIP)?
Yes, W25Q128JWFIQ supports execute-in-place (XIP) operation using Dual or Quad SPI instructions such as Fast Read Dual I/O (BBh) and Fast Read Quad I/O (EBh). Its 133MHz Quad SPI clock and uniform 4KB sector architecture enable deterministic latency and efficient instruction fetch - widely adopted in Cortex-M and RISC-V microcontrollers with SPI memory controllers.
What package type corresponds to the 'FIQ' suffix in W25Q128JWFIQ?
The 'FIQ' suffix denotes the 8-pin SOIC 208-mil package (Package Code S) with Industrial Plus grade qualification (−40°C to +105°C). This variant includes all standard SPI, Dual SPI, and Quad SPI functionality but excludes the dedicated /RESET pin - confirming pin 7 as /HOLD/IO3 per Winbond's Revision G datasheet section 3.3.
W25Q128JWFIQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
W25Q128JWFIQ FAQ
1.How can I place an order for W25Q128JWFIQ through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JWFIQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JWFIQ reliable?
The price and inventory of W25Q128JWFIQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWFIQ is usually 5 days.
3.What payment methods are accepted for W25Q128JWFIQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWFIQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JWFIQ?
W25Q128JWFIQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JWFIQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JWFIQ?
For technical support, including W25Q128JWFIQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWFIQ requirements.
6.How does Aetrix verify that W25Q128JWFIQ is sourced from the original manufacturer or authorized distributors?
All W25Q128JWFIQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWFIQ meets industry standards.
7.What is the process for return or replacement of W25Q128JWFIQ?
All W25Q128JWFIQ units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWFIQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JWFIQ part is unused and in its original packaging.
Return procedure for W25Q128JWFIQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JWFIQ Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

