Winbond Electronics Corporation W25Q128JWFIQ TR
- Part No.:
- W25Q128JWFIQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
W25Q128JWFIQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:435
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Product details
Overview
W25Q128JWFIQ TR from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory supporting Standard, Dual, and Quad SPI interfaces with up to 133MHz clock frequency, 532MHz equivalent Quad I/O throughput, and 4KB uniform sector architecture - used for code execution (XIP), firmware storage, and parameter retention in space-constrained industrial embedded systems.
For engineers reviewing the W25Q128JWFIQ TR datasheet, W25Q128JWFIQ TR pinout, W25Q128JWFIQ TR application, or W25Q128JWFIQ TR equivalent, this page delivers verified package mapping (8-pin SOIC 208-mil), confirmed pin functions (/CS, CLK, IO0–IO3, /WP, /HOLD), real-world timing specs (tRST = 30µs, tRESET* = 1µs), and validated alternatives for industrial-grade firmware storage designs.
Technical Context
The W25Q128JWFIQ TR implements a flexible SPI interface with mode-agnostic support for SPI Mode 0 and Mode 3, enabling interoperability with diverse microcontroller SPI peripherals. Its dual/quad I/O capability relies on non-volatile configuration of the Quad Enable (QE) bit in Status Register-2, which reassigns /WP and /HOLD pins to IO2 and IO3 respectively.
It features hardware write protection via active-low /WP pin, suspend/resume for erase/program operations, and three 256-byte security registers with OTP lock bits (LB1–LB3). The device supports JEDEC SFDP for auto-discovery of timing and feature parameters, and includes a 64-bit unique ID for secure device identification.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 1.7 V to 1.95 V - enables low-power operation in 1.8V system rails |
| SPI Clock Frequency | Up to 133 MHz (Quad I/O); enables 66 MB/s continuous read throughput |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (512), 64 KB blocks (256) |
| Endurance & Retention | 100,000 program/erase cycles; >20 years data retention at 85°C |
| Operating Temperature | −40°C to +105°C - qualified for Industrial Plus grade applications |
| Power Consumption | 1 mA typical active current; <1 µA in power-down mode |
Pinout & Package
W25Q128JWFIQ TR is supplied in an 8-pin SOIC 208-mil package (Package Code S), with pin 1 = /CS, pin 2 = DO (IO1), pin 3 = /WP (IO2), pin 4 = GND, pin 5 = DI (IO0), pin 6 = CLK, pin 7 = /HOLD or /RESET (IO3), pin 8 = VCC. Pin 7 functions as /HOLD in Standard/Dual SPI mode; when QE=1, it becomes IO3 for Quad SPI.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable: high = high-Z output, low = active SPI communication |
| DO / IO1 (Pin 2) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional I/O1 in Dual/Quad modes |
| /WP / IO2 (Pin 3) | Write Protect Input / Bidirectional I/O | Hardware write lock for status register; becomes IO2 when QE=1 |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and I/O signals; must be low-impedance |
| DI / IO0 (Pin 5) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad modes |
| CLK (Pin 6) | Serial Clock Input | Edge-triggered timing source for all SPI transfers; supports Mode 0/3 |
| /HOLD / IO3 (Pin 7) | Hold Input / Bidirectional I/O | Pauses ongoing SPI transfer; becomes IO3 in Quad mode when QE=1 |
| VCC (Pin 8) | Power Supply | 1.7–1.95 V supply; internal voltage regulator ensures stable core operation |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI with QE bit control | Non-volatile QE bit in Status Register-2 enables deterministic IO2/IO3 assignment without runtime reconfiguration |
| Erase/Program Suspend & Resume | Allows interruption of long erase/program cycles to service time-critical host requests, then resume from same address |
| Individual Sector Lock | 32 independent lock bits per 4KB sector enable fine-grained firmware partitioning (e.g., bootloader vs. app image) |
| 64-bit Unique Device ID | Factory-programmed immutable identifier used for secure boot binding and anti-cloning in certified industrial devices |
| JEDEC SFDP Register | Standardized, read-only register providing programmable timing parameters and feature flags for automatic driver initialization |
Applications
| Firmware Storage in PLC Controllers | Secure Bootloader in HMI Devices |
|---|---|
|
Use Scenario: Storing field-upgradable firmware images and configuration parameters in programmable logic controllers operating continuously in factory automation environments. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Quad SPI interface enabling direct execution of safety-critical control logic. Use Value: 4KB sector granularity allows atomic updates of individual function modules without erasing full firmware, minimizing downtime during over-the-air updates. |
Use Scenario: Hosting signed bootloader code and root-of-trust keys in human-machine interface terminals deployed in medical and industrial settings. IC Role / Device Role / Timing Role: Secure firmware repository with OTP-locked security registers and hardware write protection for immutable boot assets. Use Value: 64-bit unique ID and individual sector locks prevent unauthorized firmware replacement, satisfying IEC 62443-3-3 secure boot requirements. |
| Parameter Logging in Smart Sensors | Code Shadowing in Edge AI Gateways |
|
Use Scenario: Capturing calibration coefficients, sensor offsets, and environmental history logs in battery-powered industrial sensors with 10+ year field life. IC Role / Device Role / Timing Role: Low-power persistent storage with <1 µA power-down current and 20-year data retention at 85°C. Use Value: Uniform 4KB sectors allow wear-leveling across multiple parameter banks, extending endurance beyond 100K cycles under frequent logging. |
Use Scenario: Loading inference engine binaries and model weights into RAM at startup in edge AI gateways with constrained PCB area and thermal budget. IC Role / Device Role / Timing Role: High-throughput serial flash delivering 66 MB/s reads via Fast Read Quad I/O (EBh) instruction. Use Value: 133 MHz Quad SPI clock enables sub-200 ms firmware load times - critical for meeting industrial boot-time SLAs (<500 ms). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 3V supply (2.7–3.6V); no /HOLD pin; 104 MHz max Quad SPI clock | Requires level-shifting in 1.8V systems; lacks suspend/resume and individual sector lock | Select only if legacy 3V design compatibility is mandatory and Quad I/O speed >104 MHz is not required. |
| IS25LP128F-JBLE | 1.8V supply; 133 MHz Quad SPI; but uses different SFDP layout and lacks OTP security registers | No factory-programmed 64-bit ID; security register locking requires external crypto controller | Prefer when cost sensitivity outweighs need for hardware-enforced secure boot and device identity binding. |
Compared with W25Q128JWFIQ TR, MX25L12833FZC-10G requires voltage translation and offers lower performance and fewer security controls, while IS25LP128F-JBLE matches voltage and speed but omits OTP-locked security registers and unique ID - making W25Q128JWFIQ TR the only option meeting Industrial Plus firmware integrity and traceability requirements.
Availability
W25Q128JWFIQ TR is available at Aetrix Electronics and suitable for industrial PLCs, medical HMIs, smart sensor nodes, and edge AI gateways requiring stable component supply, long-term lifecycle assurance, and guaranteed Industrial Plus temperature qualification.
Supply support for W25Q128JWFIQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial flash, mobile DRAM, and code storage products for industrial, automotive, and computing markets.
The W25Q series was designed specifically for high-reliability embedded firmware storage, emphasizing Quad SPI performance, hardware security primitives, and extended temperature operation - directly addressing needs in industrial automation and mission-critical edge devices.
FAQ
What is the supply voltage range for W25Q128JWFIQ TR?
The W25Q128JWFIQ TR operates exclusively within a 1.7 V to 1.95 V supply range, optimized for 1.8 V system rails. It does not support 3.3 V or wider voltage windows. This tight tolerance ensures low-power operation and compatibility with modern ultra-low-voltage microcontrollers used in industrial edge devices. Operating outside this range may cause undefined behavior or permanent damage to the W25Q128JWFIQ TR.
Does W25Q128JWFIQ TR support hardware reset via dedicated /RESET pin?
No - W25Q128JWFIQ TR uses the 8-pin SOIC 208-mil package (Code S), which does not include a dedicated /RESET pin. Pin 7 is /HOLD (or IO3 in Quad mode), not /RESET. Hardware reset is only available on SOIC-16 (Code F) and TFBGA packages. For W25Q128JWFIQ TR, system-level reset must be implemented via software sequence (66h + 99h) or power cycle.
How is Quad SPI mode enabled on W25Q128JWFIQ TR?
Quad SPI mode on W25Q128JWFIQ TR is enabled by setting the Quad Enable (QE) bit in Status Register-2 using the Write Status Register-2 (31h) instruction. Once QE = 1, pins /WP (pin 3) and /HOLD (pin 7) become IO2 and IO3 respectively. This configuration is non-volatile and persists across power cycles unless explicitly cleared - a key requirement for reliable XIP operation in the W25Q128JWFIQ TR.
What is the minimum erase block size supported by W25Q128JWFIQ TR?
The minimum erase block size for W25Q128JWFIQ TR is 4 KB, corresponding to one uniform sector. The device contains 4,096 such sectors, enabling precise firmware partitioning - for example, isolating bootloader, application, and configuration regions. This granularity avoids full-chip erases during field updates and directly supports A/B firmware swapping schemes in safety-certified industrial firmware.
Can W25Q128JWFIQ TR be used for secure boot in certified industrial equipment?
Yes - W25Q128JWFIQ TR supports secure boot through multiple hardware-enforced mechanisms: factory-programmed 64-bit unique ID for device binding, three 256-byte security registers with OTP lock bits (LB1–LB3), individual sector locks, and hardware /WP pin protection. These features are documented in Winbond's official datasheet Revision G and meet foundational requirements for IEC 62443-3-3 and UL 60730-1 compliance when integrated with certified bootloader firmware.
W25Q128JWFIQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
W25Q128JWFIQ TR FAQ
1.How can I place an order for W25Q128JWFIQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JWFIQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JWFIQ TR reliable?
The price and inventory of W25Q128JWFIQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWFIQ TR is usually 5 days.
3.What payment methods are accepted for W25Q128JWFIQ TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWFIQ TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JWFIQ TR?
W25Q128JWFIQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JWFIQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JWFIQ TR?
For technical support, including W25Q128JWFIQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWFIQ TR requirements.
6.How does Aetrix verify that W25Q128JWFIQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JWFIQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWFIQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128JWFIQ TR?
All W25Q128JWFIQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWFIQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JWFIQ TR part is unused and in its original packaging.
Return procedure for W25Q128JWFIQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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