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Winbond Electronics Corporation W25Q128JWPIM

Part No.:
W25Q128JWPIM
Manufacturer:
Winbond Electronics Corporation
Category:
Memory
Package:
8-WDFN Exposed Pad
Datasheet:
AetrixW25Q128JWPIM.pdf
Description:
IC FLASH 128MBIT SPI/QUAD 8WSON
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:3,020

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Product details

Overview

W25Q128JWPIM from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI interface, supporting up to 133MHz Quad I/O clocking for 532Mbps effective throughput. It features uniform 4KB sectors, 100K program-erase cycles, and 20-year data retention. Designed for code execution (XIP), firmware storage, and parameter logging in space-constrained industrial systems.

For engineers reviewing the W25Q128JWPIM datasheet, W25Q128JWPIM pinout, W25Q128JWPIM application, or W25Q128JWPIM equivalent, key selection factors include Quad SPI timing compliance, /WP and /HOLD pin behavior in standard vs. Quad mode, sector protection granularity, and package-specific /RESET availability in SOIC-16 or TFBGA variants.

Technical Context

The W25Q128JWPIM implements a flexible SPI command architecture supporting Standard (4-wire), Dual (2 I/O lines), and Quad (4 I/O lines) protocols - with Quad operation enabled only when the non-volatile QE bit in Status Register-2 is set. Its internal block diagram includes a 65,536-page (256-byte/page) array, configurable erase units (4KB sector / 32KB block / 64KB block / chip), and dual-mode I/O pins (DI/DO → IO0–IO3).

Hardware reset is not available on the W25Q128JWPIM package (8-pin SOIC 208-mil, Package Code S); /HOLD functionality remains active in Standard/Dual modes but is repurposed as IO3 in Quad mode. Write protection combines volatile/non-volatile status register bits (BP2–BP0, TB, SEC, CMP, SRP) with hardware /WP pin control and OTP-locked security registers.

Key Specifications

Parameter Value and Actual Design Meaning
Memory Density 128 M-bit (16 MB), organized as 65,536 × 256-byte pages
Supply Voltage 1.7–1.95 V - enables low-power operation in battery-backed or energy-sensitive industrial designs
Quad SPI Clock Rate Up to 133 MHz - delivers 532 Mbps effective bandwidth using Fast Read Quad I/O (EBh)
Erase Granularity Uniform 4 KB sectors (4,096 total), plus 32 KB and 64 KB blocks - supports fine-grained firmware partitioning
Endurance & Retention 100,000 program-erase cycles per sector; >20 years data retention at 85°C
Operating Temperature −40°C to +85°C (Industrial Grade) - validated for extended thermal cycling in embedded controllers
Active/Power-down Current 1 mA typical active current; <1 µA typical power-down current - critical for always-on sensor nodes

Pinout & Package

W25Q128JWPIM uses the 8-pin SOIC 208-mil package (Package Code S), with no dedicated /RESET pin. Pin functions are shared across SPI modes: /CS enables device selection; DI/DO serve as IO0/IO1 in Dual mode; /WP and /HOLD become IO2/IO3 in Quad mode when QE=1.

Pin Circuit Role Design Meaning
1 /CS Chip Select Input Active-low enable; high-impedance DO during deselect; must transition high→low after power-up to accept new instructions
2 DO (IO1) Data Output / Bidirectional I/O Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad modes; high-Z when /CS high or /HOLD low
3 /WP (IO2) Write Protect Input / Bidirectional I/O Active-low hardware lock for status register; becomes IO2 in Quad mode when QE=1; requires external pull-up if unused
4 GND Ground Reference Primary return path for VCC and I/O signals; must be low-impedance to maintain signal integrity at 133 MHz
5 DI (IO0) Data Input / Bidirectional I/O Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad modes; sampled on rising CLK edge
6 CLK Serial Clock Input Edge-triggered timing reference; supports SPI Mode 0 and Mode 3; max 133 MHz in Quad I/O configuration
7 /HOLD (IO3) Hold Input / Bidirectional I/O Pauses ongoing read/write without deselecting; becomes IO3 in Quad mode when QE=1; active-low with internal pull-up
8 VCC Power Supply 1.7–1.95 V supply; must ramp monotonically; /CS tracking required during power-up/power-down per datasheet Figure 58

Key Features

Feature Design Value
Erase/Program Suspend & Resume Allows interruption of long erase/program operations to service time-critical reads - essential for real-time firmware updates
64-bit Unique ID Factory-programmed per-device identifier accessible via Read Unique ID (4Bh) - enables secure device binding and anti-cloning
Discoverable Parameters (SFDP) Standardized JEDEC JESD216-compliant register (5Ah) - enables automatic driver configuration without hard-coded timing tables
Three 256-byte Security Registers OTP-lockable storage for keys, calibration data, or license tokens - protected by LB1–LB3 bits and write-disable mechanisms
Volatile & Non-volatile Status Control Configurable BP, TB, SEC, CMP, SRP bits allow mixed protection schemes - e.g., non-volatile sector locks + volatile write-enable latching

Applications

Firmware Storage in PLCs Boot Code Execution (XIP)

Use Scenario: Storing field-upgradable ladder logic and HMI assets in programmable logic controllers operating in factory-floor environments with wide temperature swings and EMI.

IC Role / Device Role / Timing Role: Non-volatile firmware repository with deterministic 4KB sector erase - enabling atomic firmware patching without runtime interruption.

Use Value: 100K endurance and −40°C to +85°C rating ensure reliable reprogramming over 10+ years of industrial deployment.

Use Scenario: Executing boot loader and real-time OS kernel directly from flash on ARM Cortex-M7 microcontrollers in medical imaging subsystems.

IC Role / Device Role / Timing Role: XIP-capable Quad SPI memory delivering 66 MB/s continuous read throughput - eliminating RAM copy latency during cold start.

Use Value: 133 MHz Quad I/O clocking reduces boot time by >4× versus standard SPI, meeting strict FDA-required power-on self-test deadlines.

Secure Parameter Logging Edge AI Model Storage

Use Scenario: Recording calibrated sensor offsets, compensation coefficients, and audit logs in smart grid meters with tamper-detection requirements.

IC Role / Device Role / Timing Role: Secure storage node leveraging OTP-locked security registers and individual sector locks - preventing unauthorized parameter modification.

Use Value: 64-bit unique ID and SFDP register enable cryptographic binding of calibration data to specific hardware instances.

Use Scenario: Hosting quantized neural network weights and inference metadata in battery-powered predictive maintenance gateways deployed on rotating machinery.

IC Role / Device Role / Timing Role: High-bandwidth, low-power memory for loading model layers on-demand - minimizing wake-up time and extending battery life.

Use Value: <1 µA power-down current and 4KB sector granularity allow selective model layer erasure without disturbing inference engine code.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash applications.

Alternative Part Technical Difference Application Difference Selection Advice
MX25L12835FZC-10G 3V supply (2.7–3.6V), no /HOLD pin in 8-pin SOIC, 104MHz max Quad SPI clock Lacks 1.8V compatibility and 133MHz performance; unsuitable for ultra-low-power or high-throughput XIP Select only if system already uses 3V rail and bandwidth demand ≤ 416 Mbps
S25FL128SAGMFV001 1.8V compatible, 108MHz Quad SPI, includes dedicated /RESET in all packages, no /HOLD pin Offers hardware reset on every variant but sacrifices /HOLD functionality - limits multi-device SPI bus arbitration Prefer when deterministic hardware reset is mandatory and /HOLD is unused in the design

Compared with W25Q128JWPIM, MX25L12835FZC-10G requires voltage translation in 1.8V systems and delivers 22% lower Quad bandwidth, while S25FL128SAGMFV001 trades /HOLD capability for universal /RESET - making W25Q128JWPIM optimal for 1.8V, high-speed, multi-drop SPI applications needing both hold and quad performance.

Availability

W25Q128JWPIM is available at Aetrix Electronics and suitable for industrial PLC firmware storage, medical device boot code execution, smart meter parameter logging, and edge AI model hosting requiring stable component supply across extended product lifecycles.

Supply support for W25Q128JWPIM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including serial flash, mobile DRAM, and code storage devices for industrial and automotive markets.

The W25Q series targets high-reliability embedded systems requiring fast, secure, and low-voltage non-volatile storage - with W25Q128JWPIM optimized for industrial-grade 1.8V operation and Quad SPI performance.

FAQ

Does W25Q128JWPIM support hardware reset?

No, W25Q128JWPIM does not support hardware reset. It uses the 8-pin SOIC 208-mil package (Code S), which lacks a dedicated /RESET pin. Reset functionality is available only via software sequence (66h + 99h) or on alternate packages like SOIC-16 (F) and TFBGA (B/C). The /HOLD pin on W25Q128JWPIM remains functional in Standard/Dual SPI but becomes IO3 in Quad mode.

What is the maximum Quad SPI clock frequency for W25Q128JWPIM?

The W25Q128JWPIM supports up to 133 MHz Quad SPI clock frequency, enabling 532 Mbps effective data transfer using Fast Read Quad I/O (EBh) instruction. This specification is guaranteed under Industrial Grade conditions (−40°C to +85°C) with proper signal integrity layout and VCC = 1.7–1.95 V.

How does the /WP pin function in Quad SPI mode on W25Q128JWPIM?

On W25Q128JWPIM, the /WP pin becomes IO2 in Quad SPI mode when the Quad Enable (QE) bit in Status Register-2 is set to 1. Hardware write protection is disabled in this mode. To retain /WP functionality, QE must remain cleared - limiting operation to Standard or Dual SPI. The /WP pin is active-low and requires an external pull-up resistor when unused.

Can W25Q128JWPIM execute code directly from flash (XIP)?

Yes, W25Q128JWPIM supports execute-in-place (XIP) operation via Dual and Quad SPI interfaces. Fast Read Dual I/O (BBh) and Fast Read Quad I/O (EBh) instructions enable high-bandwidth sequential reads required for real-time code execution. XIP performance depends on host controller support for continuous read modes and proper cache coherency handling.

What package type does W25Q128JWPIM use, and what are its key mechanical dimensions?

W25Q128JWPIM uses the 8-pin SOIC 208-mil package (Package Code S), measuring 5.3 mm × 5.3 mm × 1.95 mm (L × W × H) with 1.27 mm lead pitch. This compact, surface-mount package is RoHS-compliant and qualified for reflow soldering per J-STD-020. It does not include a /RESET pin and shares /HOLD and /WP pins with IO3 and IO2 in Quad mode.

W25Q128JWPIM Specifications

Product attributes
Attribute value
Manufacturer:
Winbond Electronics Corporation
Series:
SpiFlash®
Package/Case:
8-WDFN Exposed Pad
Packaging:
Tube
Product Status:
Active
Programmable:
Not Verified
Memory Type:
Non-Volatile
Memory Format:
FLASH
Technology:
FLASH - NOR
Memory Size:
128Mbit
Memory Organization:
16M x 8
Memory Interface:
SPI - Quad I/O
Clock Frequency:
133 MHz
Write Cycle Time - Word, Page:
-, 3ms
Access Time:
-
Voltage - Supply:
1.7V ~ 1.95V
Operating Temperature:
-40°C ~ 85°C (TA)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
8-WSON (6x5)

W25Q128JWPIM FAQ

1.How can I place an order for W25Q128JWPIM through Aetrix?

Please submit a Request for Quotation (RFQ) for W25Q128JWPIM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for W25Q128JWPIM reliable?

The price and inventory of W25Q128JWPIM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWPIM is usually 5 days.

3.What payment methods are accepted for W25Q128JWPIM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWPIM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for W25Q128JWPIM?

W25Q128JWPIM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your W25Q128JWPIM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for W25Q128JWPIM?

For technical support, including W25Q128JWPIM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWPIM requirements.

6.How does Aetrix verify that W25Q128JWPIM is sourced from the original manufacturer or authorized distributors?

All W25Q128JWPIM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWPIM meets industry standards.

7.What is the process for return or replacement of W25Q128JWPIM?

All W25Q128JWPIM units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWPIM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The W25Q128JWPIM part is unused and in its original packaging.

Return procedure for W25Q128JWPIM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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