My Inquiry
My Account
Winbond Electronics Corporation W25Q128JWYIR TR
- Part No.:
- W25Q128JWYIR TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 21-XFBGA, WLCSP
- Datasheet:
-
W25Q128JWYIR TR.pdf
- Description:
- IC FLASH 128MBIT SPI 21WLCSP
- Quantity:
- Payment:
- Shipping:
Inventory:1,155
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128JWYIR TR from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI, QPI, and DTR read support, organized as 65,536 × 256-byte pages. It delivers up to 133MHz Quad I/O clocking, 532MHz equivalent bandwidth, and 66MB/s continuous read throughput. Designed for code execution (XIP), firmware storage, and parameter retention in space-constrained industrial systems.
For engineers reviewing the W25Q128JWYIR TR datasheet, W25Q128JWYIR TR pinout, W25Q128JWYIR TR application, or W25Q128JWYIR TR equivalent, key selection criteria include its 1.7–1.95V supply range, hardware /WP and /HOLD pins (in non-Quad mode), 4KB uniform sector architecture, JEDEC ID and 64-bit unique ID support, and industrial temperature rating (–40°C to +105°C).
Technical Context
The W25Q128JWYIR TR implements a flexible SPI command set supporting Standard, Dual, Quad, and QPI protocols - with Quad Enable (QE) bit in Status Register-2 controlling IO2 (/WP) and IO3 (/HOLD) remapping. Its DTR (Double Transfer Rate) mode enables high-speed reads using both clock edges, achieving 532MHz effective throughput under Quad I/O Fast Read instructions (EDh).
It features three 256-byte Security Registers with OTP locks, programmable block/sector protection (BP2–BP0, TB, SEC, CMP), Erase/Program Suspend & Resume, and SFDP (Serial Flash Discoverable Parameters) register for runtime configuration discovery. The device supports hardware reset only on packages with dedicated /RESET (e.g., SOIC-16, TFBGA), while 8-pin variants use IO3 for /HOLD or configurable /RESET via status bits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 1.7 V to 1.95 V - enables low-power operation in 1.8V system rails |
| Max Clock Frequency | 133 MHz Quad I/O - enables 532 Mbps effective data rate with EDh instruction |
| Read Throughput | 66 MB/s continuous - exceeds X16 parallel flash in bandwidth-per-pin efficiency |
| Erase Granularity | 4 KB sectors, 32 KB blocks, 64 KB blocks, full chip - supports fine-grained firmware partitioning |
| Data Retention | 20+ years - validated for long-life industrial deployments without refresh |
| Endurance | 100,000 program-erase cycles per sector - suitable for frequent firmware updates |
| Operating Temp | –40°C to +105°C - qualified for Industrial Plus grade applications |
Pinout & Package
W25Q128JWYIR TR is supplied in an 8-pad WSON 6×5-mm package (Package Code P), with exposed pad for thermal dissipation. Pin 1 = /CS, Pin 2 = DO (IO1), Pin 3 = /WP (IO2), Pin 4 = GND, Pin 5 = DI (IO0), Pin 6 = CLK, Pin 7 = /HOLD or /RESET (IO3), Pin 8 = VCC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable; places DO/IOs in high-Z when deasserted; required high-to-low transition after power-up before instruction acceptance |
| DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional I/O1 in Dual/Quad modes; used for status/data reads on falling CLK edge |
| /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware lock for Status Register writes when QE=0; becomes IO2 in Quad mode (QE=1); active-low |
| GND | Ground Reference | Primary signal and power return path; must be low-impedance for stable timing and noise immunity |
| DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional I/O0 in Dual/Quad modes; accepts instructions/addresses on rising CLK edge |
| CLK | Serial Clock Input | Master-synchronized timing source; all SPI transfers referenced to this edge-triggered signal |
| /HOLD or /RESET (IO3) | Hold Input / Reset Input / Bidirectional I/O | Pauses ongoing transfers when low (active-low HOLD); functions as hardware reset only if configured via status register (QE=0) or on dedicated /RESET packages |
| VCC | Power Supply | 1.7–1.95 V core supply; requires local 100nF decoupling; tracks /CS during power sequencing |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead by encoding commands in 4-bit nibbles; enables true XIP with deterministic latency |
| Read Command Bypass with Wrap | Eliminates repeated address transmission; allows continuous burst reads with wrap-around addressing in ≤8 clocks |
| DTR (Double Transfer Rate) Read | Uses both rising and falling edges of CLK in Quad I/O mode (EDh/BDh), doubling effective bandwidth without increasing clock frequency |
| Individual Block/Sector Lock | Enables per-sector write-protection via 36h/39h instructions - critical for secure bootloader and configuration partitioning |
| Security Registers (3 × 256B) | OTP-lockable storage for keys, certificates, or calibration data; isolated from main array and protected by LB1–LB3 bits |
| SFDP Register Support | Provides standardized, runtime-discoverable parameters (timing, density, erase types) - simplifies driver portability across flash vendors |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Bootloader |
|---|---|
Use Scenario: Storing and executing boot firmware and real-time control logic in programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP capability; provides deterministic 66MB/s read throughput for fast boot and low-latency interrupt response. Use Value: 20-year data retention and 100K endurance ensure firmware integrity over extended maintenance cycles without field replacement. |
Use Scenario: Hosting safety-critical bootloader and sensor fusion firmware in automotive camera or radar ECUs requiring ASIL-B alignment. IC Role / Device Role / Timing Role: Secure firmware repository with individual sector locking (36h/39h) and 64-bit unique ID for anti-cloning and version traceability. Use Value: –40°C to +105°C operation and hardware /WP pin support meet AEC-Q100 Grade 2 thermal requirements for under-hood deployment. |
| Medical Imaging Device Configuration | Edge AI Gateway Parameter Storage |
Use Scenario: Storing calibrated imaging parameters, DICOM metadata templates, and regulatory audit logs in portable ultrasound or X-ray units. IC Role / Device Role / Timing Role: High-reliability parameter store with 4KB sector granularity enabling independent update of calibration tables without disturbing image processing firmware. Use Value: Three OTP-locked 256-byte Security Registers protect encryption keys used for HIPAA-compliant data-at-rest encryption. |
Use Scenario: Holding neural network weights, model version identifiers, and OTA update staging buffers in compact industrial gateways running TensorFlow Lite Micro. IC Role / Device Role / Timing Role: High-bandwidth firmware and data buffer; leverages DTR Fast Read Quad I/O (EDh) to feed inference engines at >60 MB/s sustained rates. Use Value: SFDP register enables automatic driver adaptation across multiple flash generations - reducing BOM management effort during product lifecycle transitions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 3V supply (2.7–3.6V); no DTR support; max 104MHz Quad SPI; lacks SFDP and security registers | Requires separate voltage rail; unsuitable for 1.8V-only designs or DTR-dependent high-throughput pipelines | Select only if legacy 3V infrastructure exists and security/SFDP features are unnecessary |
| S25FL128SAGMFI000 | 1.8V supply; supports DTR; includes HyperBus interface option; higher pin count (16-pin SOIC); integrated ECC | Offers HyperBus for even higher bandwidth but increases PCB footprint and layout complexity | Prefer when migrating to HyperFlash-compatible platforms or requiring on-die ECC for extended reliability |
Compared with MX25L12833FZC-10G and S25FL128SAGMFI000, the W25Q128JWYIR TR uniquely balances 1.8V operation, DTR-enabled 532Mbps throughput, SFDP discoverability, and OTP-secured registers - making it optimal for new industrial and automotive designs prioritizing integration density and firmware security.
Availability
W25Q128JWYIR TR is available at Aetrix Electronics and suitable for industrial PLCs, automotive ADAS modules, medical imaging devices, and edge AI gateways requiring stable component supply across extended product lifecycles.
Supply support for W25Q128JWYIR TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash, RAM, and mobile DRAM, serving industrial, automotive, and consumer markets.
The W25Q series targets high-performance, low-voltage embedded systems requiring reliable code storage, XIP execution, and advanced security - with W25Q128JWYIR TR optimized for industrial-plus temperature and DTR-enhanced throughput.
FAQ
What is the package type and footprint of W25Q128JWYIR TR?
W25Q128JWYIR TR uses an 8-pad WSON 6×5-mm package (Package Code P) with exposed thermal pad. It has standard 0.5-mm pitch, 2.1-mm body width, and 3.0-mm body length. This compact footprint supports high-density PCB layouts in space-constrained industrial and automotive modules, and is compatible with reflow soldering per J-STD-020.
Does W25Q128JWYIR TR support hardware reset, and how is it implemented?
W25Q128JWYIR TR does not include a dedicated /RESET pin - it uses Pin 7 (/HOLD or /RESET) in configurable mode. When Quad Enable (QE) = 0, this pin functions as /HOLD; when QE = 0 and the HOLD/RST bit (SR3[6]) is set, it operates as a hardware reset input. This behavior is documented in Section 7.1.13 of the datasheet and requires explicit status register programming.
How does the DTR (Double Transfer Rate) feature improve performance in W25Q128JWYIR TR?
W25Q128JWYIR TR's DTR mode uses both rising and falling edges of the clock signal during Quad I/O reads (e.g., EDh instruction), effectively doubling data transfer rate without raising clock frequency. At 133MHz, this yields 532Mbps throughput - enabling faster boot times and smoother streaming of firmware or media assets compared to standard Quad SPI.
Can W25Q128JWYIR TR be used for secure key storage, and what mechanisms are provided?
Yes - W25Q128JWYIR TR includes three 256-byte Security Registers (SR1–SR3) with OTP (One-Time Programmable) lock bits (LB1–LB3). Once locked, these registers become read-only and immune to accidental overwrite. They are electrically isolated from the main array and accessible only via dedicated instructions (42h/44h/48h), meeting requirements for storing cryptographic keys or calibration secrets.
What is the difference between W25Q128JWYIR TR and W25Q128JVSIM TR?
W25Q128JWYIR TR is rated for Industrial Plus grade (–40°C to +105°C) and uses WSON 6×5-mm (P-code) packaging, while W25Q128JVSIM TR is Industrial grade (–40°C to +85°C) in SOIC-208-mil (S-code). Both share identical electrical specs and instruction sets, but W25Q128JWYIR TR offers extended temperature tolerance and smaller footprint - critical for thermally demanding or size-constrained applications.
W25Q128JWYIR TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 21-XFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- 6 ns
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 21-WLCSP
W25Q128JWYIR TR FAQ
1.How can I place an order for W25Q128JWYIR TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JWYIR TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JWYIR TR reliable?
The price and inventory of W25Q128JWYIR TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWYIR TR is usually 5 days.
3.What payment methods are accepted for W25Q128JWYIR TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWYIR TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JWYIR TR?
W25Q128JWYIR TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JWYIR TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JWYIR TR?
For technical support, including W25Q128JWYIR TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWYIR TR requirements.
6.How does Aetrix verify that W25Q128JWYIR TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JWYIR TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWYIR TR meets industry standards.
7.What is the process for return or replacement of W25Q128JWYIR TR?
All W25Q128JWYIR TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWYIR TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JWYIR TR part is unused and in its original packaging.
Return procedure for W25Q128JWYIR TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JWYIR TR Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
