Winbond Electronics Corporation W25Q20CLZPIG
- Part No.:
- W25Q20CLZPIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q20CLZPIG.pdf
- Description:
- IC FLASH 2MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q20CLZPIG from Winbond is a 2M-bit (256KB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with 4KB uniform sectors, 104MHz max clock, and XIP-capable continuous read mode. It operates from 2.3V–3.6V, draws 1mA active / <1µA power-down current, and targets embedded code storage, firmware boot, and parameter logging in space-constrained MCU systems.
For engineers reviewing the W25Q20CLZPIG datasheet, W25Q20CLZPIG pinout, W25Q20CLZPIG application, or W25Q20CLZPIG equivalent, key selection considerations include Quad SPI enable (QE bit), hardware write protection via /WP and /HOLD pins, sector-level erase granularity, JEDEC ID and Unique Serial Number support, and compatibility with SOIC-8, VSOP-8, WSON-8 (6×5mm), and USON-8 (2×3mm) footprints.
Technical Context
The W25Q20CLZPIG implements a SPI-compatible command set with three operational modes: Standard (DI/DO), Dual I/O (IO0/IO1), and Quad I/O (IO0–IO3), where IO2 and IO3 are remapped from /WP and /HOLD only when the non-volatile Quad Enable (QE) bit in Status Register-2 is set. Its architecture supports true execute-in-place (XIP) via Continuous Read Mode with ≤8-clock instruction overhead for 24-bit address access.
Write protection combines volatile (WEL latch) and non-volatile mechanisms (BP2–BP0, TB, SEC, CMP, SRP0/SRP1 bits) plus hardware control via active-low /WP and /HOLD pins - though both are repurposed as IO2/IO3 in Quad mode. Erase flexibility includes 4KB sectors, 32KB blocks, and 64KB blocks, with ≥100,000 program/erase cycles and >20-year data retention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 2 M-bit (256 KB), organized as 1,024 × 256-byte pages |
| Interface Support | Standard/Dual/Quad SPI; requires QE=1 for Quad I/O; supports Modes 0 & 3 |
| Max Clock Frequency | 104 MHz (208 Mbps Dual I/O, 416 Mbps Quad I/O) |
| Erase Granularity | Uniform 4KB sectors (64 total), plus 32KB (8) and 64KB (4) blocks |
| Supply Voltage | 2.3 V to 3.6 V; enables single-rail operation with most 3.3V MCUs |
| Power Consumption | 1 mA typical active current; <1 µA in power-down mode |
| Data Retention | Greater than 20 years at +25°C; validated per JEDEC JESD22-A117 |
| Operating Temperature | −40°C to +85°C industrial grade range |
Pinout & Package
W25Q20CLZPIG is packaged in an 8-pad USON (2×3 mm, package code UX), with exposed pad for thermal dissipation and footprint compatibility with high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable; must transition high→low after power-up before first instruction |
| IO1 (DO) | Serial Data Output / Bidirectional I/O | Output in Standard SPI; IO1 in Dual/Quad modes; high-impedance when /CS high or /HOLD active |
| IO2 (/WP) | Write Protect Input / Bidirectional I/O | Hardware write lock for status register; becomes IO2 only when QE=1 (Quad mode) |
| GND | Ground Reference | Primary return path for VCC and I/O signals; requires low-impedance PCB plane |
| IO0 (DI) | Serial Data Input / Bidirectional I/O | Input in Standard SPI; IO0 in Dual/Quad modes; used for all instruction/address/data input |
| CLK | Serial Clock Input | Edge-triggered timing reference; supports Modes 0 and 3; must be stable during /CS low |
| IO3 (/HOLD) | Hold Input / Bidirectional I/O | Pauses ongoing SPI transfer; becomes IO3 only when QE=1 (Quad mode); active-low |
| VCC | Power Supply | 2.3–3.6 V supply; decoupling capacitor (0.1 µF) required within 5 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI Enable (QE bit) | Non-volatile configuration enabling 4-line I/O for 416 Mbps throughput; requires Write Status Register to set |
| Continuous Read Mode | Enables true XIP with ≤8-clock instruction overhead per 24-bit address; eliminates repeated opcode transmission |
| Hardware Write Protection | /WP pin disables status register writes independently of software BP bits; active-low, compatible with MCU GPIO |
| Unique 64-bit Serial ID | Factory-programmed, read-only identifier supporting device authentication and firmware binding per unit |
| Erase/Program Suspend | Allows pausing long erase/program operations to service interrupts; resumes without data loss or re-initialization |
| JEDEC ID & Manufacturer ID | Standard 0x9F command returns 0xEF4013 (Winbond, 2M-bit density); ensures bootloader compatibility across SPI flash vendors |
Applications
| MCU Boot Code Storage | Firmware Over-the-Air (OTA) Update |
|---|---|
Use Scenario: Storing primary bootloader and application firmware for ARM Cortex-M or RISC-V microcontrollers requiring fast, reliable non-volatile code storage. IC Role / Device Role / Timing Role: Serial NOR flash providing XIP-capable instruction fetch directly from SPI bus; supports dual/quad read for sub-100ms firmware load times. Use Value: Eliminates need for parallel NOR or external RAM shadowing; reduces BOM cost and PCB area while maintaining deterministic boot latency. | Use Scenario: Hosting delta firmware images and secure update staging areas in IoT edge devices with constrained memory and intermittent connectivity. IC Role / Device Role / Timing Role: Parameter- and code-storage device with sector-level erase isolation; enables atomic swap between active/inactive firmware banks. Use Value: Enables safe rollback on failed updates using 4KB sector granularity; supports cryptographic signature verification prior to commit. |
| Industrial Sensor Calibration Data | Human-Machine Interface (HMI) Configuration |
Use Scenario: Retaining factory-trimmed sensor offset/gain coefficients and runtime calibration history in programmable logic controllers and precision measurement equipment. IC Role / Device Role / Timing Role: Non-volatile parameter store with >20-year retention and 100k+ write cycles; accessed via SPI during sensor initialization or maintenance mode. Use Value: Ensures metrological traceability across product lifetime; avoids recalibration after power loss or firmware reload. | Use Scenario: Storing display themes, language packs, button mapping profiles, and user preferences in medical monitors and industrial HMIs. IC Role / Device Role / Timing Role: Persistent configuration storage with hardware /WP pin locking to prevent accidental overwrite during field service. Use Value: Guarantees UI consistency across reboots and firmware upgrades; allows field technicians to restore settings without host MCU intervention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L2006EZUI-12G | Same 2M-bit density, 104MHz clock, SOIC-8/WSON-8 packages; supports standard/Dual SPI but no Quad SPI or QE bit | Lacks Quad I/O and Continuous Read Mode; lower max throughput (208 Mbps vs 416 Mbps) | Select when Quad interface and XIP optimization are unnecessary; preferred for legacy SPI-only designs |
| S25FL032P0XMFI001 | 32M-bit density (16× larger), 80MHz clock, supports Quad SPI and XIP; requires different voltage (2.7–3.6V) and has distinct status register layout | Higher capacity suits complex firmware; wider VCC range improves noise margin; not drop-in due to size and register differences | Choose for future-proofing or multi-image storage; requires firmware driver update and PCB layout revision |
Compared with MX25L2006EZUI-12G, W25Q20CLZPIG delivers double the data rate in Quad mode and enables faster XIP execution; versus S25FL032P0XMFI001, it offers smaller footprint and lower power but requires careful register-level migration for status/control logic.
Availability
W25Q20CLZPIG is available at Aetrix Electronics and suitable for MCU boot code storage, OTA firmware updates, and industrial calibration data logging requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for W25Q20CLZPIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions including NOR/NAND flash, RAM, and mobile DRAM, serving automotive, industrial, and consumer markets since 1987.
The W25Q series is designed for embedded systems requiring high-speed, low-power, and pin-efficient code and data storage - emphasizing SPI protocol compliance, XIP readiness, and robust write protection for mission-critical firmware.
FAQ
What is the package type and footprint of W25Q20CLZPIG?
W25Q20CLZPIG uses an 8-pad USON package measuring 2 mm × 3 mm (package code UX), with exposed thermal pad. It is pin-compatible with other USON-8 variants in the W25Q20CL family and requires standard reflow profile for lead-free assembly. Footprint dimensions and solder mask specifications are defined in Winbond's Package Outline Drawing WSON-UX-8.
Does W25Q20CLZPIG support Quad SPI mode out of the box?
No - W25Q20CLZPIG requires the Quad Enable (QE) bit in Status Register-2 to be set via Write Status Register instruction before Quad SPI commands (e.g., 0x6B, 0xEB) become functional. By default, QE = 0; /WP and /HOLD remain dedicated hardware control pins until QE is explicitly enabled and locked.
How many program/erase cycles does W25Q20CLZPIG guarantee?
W25Q20CLZPIG guarantees a minimum of 100,000 program/erase cycles per sector, validated per JEDEC JESD22-A117. This applies uniformly across all 4KB sectors, 32KB blocks, and 64KB blocks. Endurance is maintained under specified operating conditions (−40°C to +85°C, VCC = 2.3–3.6 V).
Can W25Q20CLZPIG be used for execute-in-place (XIP) applications?
Yes - W25Q20CLZPIG supports true XIP via its Continuous Read Mode, which reduces instruction overhead to ≤8 clocks per 24-bit address. When combined with Fast Read Quad I/O (0xEB), it delivers up to 416 Mbps effective bandwidth, enabling deterministic instruction fetch directly from flash without RAM buffering in Cortex-M and similar MCUs.
What unique identifiers does W25Q20CLZPIG provide for device authentication?
W25Q20CLZPIG provides a factory-programmed, read-only 64-bit Unique Serial Number accessible via instruction 0x4B, plus standard JEDEC Manufacturer ID (0xEF) and Device ID (0x4013) via 0x9F. These identifiers support secure boot chain validation, firmware binding, and anti-cloning measures in certified industrial and medical devices.
W25Q20CLZPIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 2Mbit
- Memory Organization:
- 256K x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 800µs
- Access Time:
- -
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25Q20CLZPIG FAQ
1.How can I place an order for W25Q20CLZPIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q20CLZPIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q20CLZPIG reliable?
The price and inventory of W25Q20CLZPIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q20CLZPIG is usually 5 days.
3.What payment methods are accepted for W25Q20CLZPIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q20CLZPIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q20CLZPIG?
W25Q20CLZPIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q20CLZPIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q20CLZPIG?
For technical support, including W25Q20CLZPIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q20CLZPIG requirements.
6.How does Aetrix verify that W25Q20CLZPIG is sourced from the original manufacturer or authorized distributors?
All W25Q20CLZPIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q20CLZPIG meets industry standards.
7.What is the process for return or replacement of W25Q20CLZPIG?
All W25Q20CLZPIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q20CLZPIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q20CLZPIG part is unused and in its original packaging.
Return procedure for W25Q20CLZPIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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