Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

Winbond Electronics Corporation W25Q20EWBYIG TR

Name: W25Q20EWBYIG TR
Brand: Winbond Electronics Corporation
SKU: W25Q20EWBYIG TR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: W25Q20EWBYIG TR

Manufacturer:: Winbond Electronics Corporation

Category:: Memory

Package:: 8-XFBGA, WLCSP

Datasheet:: W25Q20EWBYIG TR.pdf

Description:: IC FLASH 2MBIT SPI/QUAD 8WLCSP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,125

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

W25Q20EWBYIG TR from Winbond is a 2 M-bit (256 KB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with 4 KB uniform sectors, 1.65–1.95 V single-supply operation, and industrial temperature range (−40°C to +85°C). It enables XIP (execute-in-place) code execution, firmware storage, and parameter logging in space-constrained embedded systems.

For engineers reviewing the W25Q20EWBYIG TR datasheet, W25Q20EWBYIG TR pinout, W25Q20EWBYIG TR application, or W25Q20EWBYIG TR equivalent, key selection considerations include Quad SPI enable (QE bit), /WP and /HOLD dual-role pin behavior in Quad mode, 104 MHz max clock frequency, 4 KB sector granularity for data partitioning, and WLCSP-8 (BY) package compatibility with high-density PCB layouts.

Technical Context

The W25Q20EWBYIG TR implements a SPI-compatible command set with three operational modes: Standard SPI (DI/DO), Dual SPI (IO0/IO1), and Quad SPI (IO0–IO3), where /WP and /HOLD become IO2 and IO3 only when the non-volatile Quad Enable (QE) bit in Status Register-2 is set. Its architecture supports erase/program suspend/resume, auto-increment read, and JEDEC-standard SFDP register access.

It features a 1,024-page array (256 bytes/page), 64 × 4 KB sectors, 8 × 32 KB blocks, and 4 × 64 KB blocks - enabling flexible firmware partitioning and field-upgrade resilience. Write protection combines volatile/non-volatile status bits (BP2–BP0, TB, SEC, CMP), hardware /WP pin control (active-low, disabled in Quad mode), and OTP-locked security registers (3 × 256-byte).

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	2 M-bit (256 KB), organized as 1,024 pages × 256 bytes - supports fine-grained firmware updates without full chip erase.
Supply Voltage	1.65 V to 1.95 V - compatible with modern low-voltage SoCs and battery-powered IoT nodes.
SPI Clock Max	104 MHz - enables up to 416 MB/s effective throughput in Quad I/O mode (104 MHz × 4), outperforming parallel flash in bandwidth-per-pin.
Erase Granularity	Uniform 4 KB sectors, plus 32 KB and 64 KB blocks - allows selective firmware patching and configuration retention during OTA updates.
Endurance & Retention	≥100,000 program/erase cycles per sector; >20 years data retention - suitable for long-life industrial controllers and automotive ECUs.
Operating Temp	−40°C to +85°C - qualified for industrial-grade deployment without derating.
Power-down Current	<1 µA (typ.) - minimizes standby power in always-on edge sensors and wearables.

Pinout & Package

W25Q20EWBYIG TR uses an 8-ball WLCSP (Wafer-Level Chip Scale Package) with 0.4 mm pitch, measuring 2.0 × 2.5 × 0.5 mm - optimized for ultra-compact PCBs and automated SMT assembly. Pin functions are identical across SOIC, VSOP, USON, and WLCSP variants per Winbond's unified pin mapping.

Pin/Terminal	Circuit Role	Design Meaning
VCC (A1)	Power supply input	1.65–1.95 V core supply; decoupling capacitor required within 1 mm for stable Quad SPI timing.
/HOLD (IO3) (A2)	Hold control / Quad I/O	Active-low pause signal in Standard/Dual SPI; becomes IO3 in Quad mode when QE=1 - requires software reconfiguration before switching modes.
/CS (A3)	Chip select input	Active-low enable; must track VCC at power-up; high-impedance DO output when deasserted.
CLK (B1)	Serial clock input	Supports SPI Modes 0 and 3; 104 MHz max; edge-triggered for instruction/data transfer synchronization.
DO (IO1) (B2)	Data output / Quad I/O	Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad modes - shared bus line requiring tri-state management.
DI (IO0) (C1)	Data input / Quad I/O	Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad modes - used for all instruction/address entry.
/WP (IO2) (C2)	Write protect / Quad I/O	Hardware lock for status register writes in Standard/Dual SPI; becomes IO2 in Quad mode when QE=1 - disables hardware write protection during Quad operation.
GND (C3)	Ground reference	Low-impedance return path; must be connected to solid ground plane to minimize SPI noise and timing jitter.

Key Features

Feature	Design Value
Quad SPI Enable (QE bit)	Non-volatile bit in Status Register-2 that permanently reassigns /WP and /HOLD to IO2/IO3 - enables 4-line data transfers without external logic.
Erase/Program Suspend	Allows pausing active erase/program operations via 75h instruction and resuming with 7Ah - critical for real-time systems handling interrupts during flash updates.
Security Registers	Three 256-byte OTP-lockable registers (with volatile/non-volatile SRP bits) - store cryptographic keys or calibration data immune to field reprogramming.
JEDEC ID & Unique Serial	Read via 9Fh (JEDEC ID) and 4Bh (64-bit unique ID) - enables secure device authentication and BOM traceability in production programming.
Auto-Increment Read	Continuous sequential reads without address retransmission - reduces host CPU overhead during firmware bootloading and image verification.

Applications

IoT Edge Node Firmware Storage	Industrial PLC Configuration Memory
Use Scenario: Storing bootloader, application firmware, and OTA update images in battery-powered wireless sensor nodes with strict size and power constraints. IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP support; delivers <1 µA standby current and 104 MHz Quad SPI read speed for fast wake-from-sleep boot. Use Value: Eliminates need for external RAM shadowing; enables sub-second firmware validation and secure boot using unique ID and SFDP register.	Use Scenario: Retaining calibrated sensor offsets, motion profiles, and safety-critical configuration parameters across power cycles in programmable logic controllers. IC Role / Device Role / Timing Role: Parameter EEPROM replacement with 4 KB sector granularity - allows independent update of calibration data without erasing control logic. Use Value: Prevents accidental overwrite via hardware /WP pin and BP bits; supports 100K+ cycles for lifetime field recalibration.
Automotive Body Control Module	Medical Wearable Data Logger
Use Scenario: Storing lighting sequences, door lock logic, and diagnostic event logs in AEC-Q100-compliant body electronics modules. IC Role / Device Role / Timing Role: Industrial-temp (-40°C to +85°C) flash memory interfacing with MCU via Quad SPI; leverages HOLD pin for bus arbitration with CAN transceivers. Use Value: Ensures data integrity under voltage transients via power-supply lock-down and tPUW power-up delay; meets automotive functional safety requirements.	Use Scenario: Capturing continuous physiological waveforms (ECG, SpO₂) and timestamped metadata in compact, rechargeable medical patches. IC Role / Device Role / Timing Role: High-reliability data buffer with 20-year retention; uses sector erase to manage circular log buffers without wear leveling firmware. Use Value: Reduces host MCU overhead via auto-increment read and suspend/resume - extends battery life by minimizing active SPI time.

IoT Edge Node Firmware Storage

Industrial PLC Configuration Memory

Use Scenario: Storing bootloader, application firmware, and OTA update images in battery-powered wireless sensor nodes with strict size and power constraints.

IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP support; delivers <1 µA standby current and 104 MHz Quad SPI read speed for fast wake-from-sleep boot.

Use Value: Eliminates need for external RAM shadowing; enables sub-second firmware validation and secure boot using unique ID and SFDP register.

Use Scenario: Retaining calibrated sensor offsets, motion profiles, and safety-critical configuration parameters across power cycles in programmable logic controllers.

IC Role / Device Role / Timing Role: Parameter EEPROM replacement with 4 KB sector granularity - allows independent update of calibration data without erasing control logic.

Use Value: Prevents accidental overwrite via hardware /WP pin and BP bits; supports 100K+ cycles for lifetime field recalibration.

Automotive Body Control Module

Medical Wearable Data Logger

Use Scenario: Storing lighting sequences, door lock logic, and diagnostic event logs in AEC-Q100-compliant body electronics modules.

IC Role / Device Role / Timing Role: Industrial-temp (-40°C to +85°C) flash memory interfacing with MCU via Quad SPI; leverages HOLD pin for bus arbitration with CAN transceivers.

Use Value: Ensures data integrity under voltage transients via power-supply lock-down and tPUW power-up delay; meets automotive functional safety requirements.

Use Scenario: Capturing continuous physiological waveforms (ECG, SpO₂) and timestamped metadata in compact, rechargeable medical patches.

IC Role / Device Role / Timing Role: High-reliability data buffer with 20-year retention; uses sector erase to manage circular log buffers without wear leveling firmware.

Use Value: Reduces host MCU overhead via auto-increment read and suspend/resume - extends battery life by minimizing active SPI time.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash memory applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MX25U2033FZUI	2 M-bit, 1.65–2.0 V, supports DTR Quad SPI but lacks OTP security registers and SFDP v1.6 compliance.	No built-in 64-bit unique ID or discoverable parameter register - limits secure provisioning and automatic driver configuration.	Prefer W25Q20EWBYIG TR when cryptographic key storage or JEDEC SFDP-based initialization is required.
AT25SF021-SSHD-B	2 M-bit, 1.7–2.0 V, includes hardware reset pin and deeper power-down mode (<100 nA), but no /HOLD pin or Quad I/O capability.	Limited to Standard/Dual SPI only - unsuitable for XIP or high-throughput firmware streaming applications.	Choose W25Q20EWBYIG TR for designs needing Quad SPI bandwidth or bus-sharing via /HOLD arbitration.

Compared with MX25U2033FZUI and AT25SF021-SSHD-B, the W25Q20EWBYIG TR uniquely combines Quad SPI I/O, OTP-secured registers, JEDEC SFDP, and industrial-temp WLCSP packaging - making it optimal for secure, space-constrained, high-speed embedded boot and logging systems.

Availability

W25Q20EWBYIG TR is available at Aetrix Electronics and suitable for IoT edge node firmware storage, industrial PLC configuration memory, and automotive body control module applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant WLCSP packaging.

Supply support for W25Q20EWBYIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including SPI NOR/NAND flash, RAM, and mobile DRAM, serving industrial, automotive, and consumer markets since 1987.

The W25Q series was designed for embedded systems demanding high reliability, low voltage operation, and advanced interface flexibility - specifically targeting code execution, secure firmware storage, and real-time parameter logging in resource-constrained environments.

FAQ

What is the package type and dimensions of the W25Q20EWBYIG TR?

The W25Q20EWBYIG TR uses an 8-ball WLCSP (Wafer-Level Chip Scale Package) with 0.4 mm ball pitch and physical dimensions of 2.0 mm × 2.5 mm × 0.5 mm. This ultra-compact package supports high-density PCB layouts and automated SMT assembly, and is explicitly designated by the "BY" package code in Winbond's ordering information.

Does the W25Q20EWBYIG TR support Quad SPI operation, and how is it enabled?

Yes, the W25Q20EWBYIG TR supports Quad SPI via instructions such as Fast Read Quad I/O (EBh), but requires the non-volatile Quad Enable (QE) bit in Status Register-2 to be set to '1'. Once enabled, the /WP and /HOLD pins become IO2 and IO3 respectively - a permanent hardware reconfiguration that must be performed before entering Quad mode.

What is the minimum and maximum supply voltage for reliable operation of the W25Q20EWBYIG TR?

The W25Q20EWBYIG TR operates reliably across a supply voltage range of 1.65 V to 1.95 V. Operation below 1.65 V may cause undefined behavior or failure to accept commands; above 1.95 V risks permanent damage. The device includes internal power-supply lock-down and tPUW power-up delay to prevent spurious writes during voltage ramp-up.

How many program/erase cycles does the W25Q20EWBYIG TR guarantee per sector?

The W25Q20EWBYIG TR guarantees a minimum of 100,000 program/erase cycles per 4 KB sector. This endurance rating applies to all sectors across the full temperature range (−40°C to +85°C) and is validated per JEDEC standards - ensuring long-term reliability in field-upgradable firmware and parameter storage applications.

Can the W25Q20EWBYIG TR be used for execute-in-place (XIP) code execution?

Yes, the W25Q20EWBYIG TR supports XIP via Dual and Quad SPI interfaces, enabling direct code execution from flash without prior loading into RAM. Its 104 MHz clock support and Fast Read Quad I/O (EBh) instruction deliver up to 416 MB/s effective throughput - making it suitable for real-time bootloaders and deterministic firmware execution in microcontroller-based systems.

W25Q20EWBYIG TR Specifications

Product attributes: Attribute value

Manufacturer:: Winbond Electronics Corporation

Series:: SpiFlash®

Package/Case:: 8-XFBGA, WLCSP

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: FLASH

Technology:: FLASH - NOR

Memory Size:: 2Mbit

Memory Organization:: 256K x 8

Memory Interface:: SPI - Quad I/O

Clock Frequency:: 104 MHz

Write Cycle Time - Word, Page:: 30µs, 800µs

Access Time:: -

Voltage - Supply:: 1.65V ~ 1.95V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-WLCSP (1.4x1.34)

W25Q20EWBYIG TR FAQ

1.How can I place an order for W25Q20EWBYIG TR through Aetrix?

Please submit a Request for Quotation (RFQ) for W25Q20EWBYIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for W25Q20EWBYIG TR reliable?

The price and inventory of W25Q20EWBYIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q20EWBYIG TR is usually 5 days.

3.What payment methods are accepted for W25Q20EWBYIG TR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q20EWBYIG TR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for W25Q20EWBYIG TR?

W25Q20EWBYIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your W25Q20EWBYIG TR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for W25Q20EWBYIG TR?

For technical support, including W25Q20EWBYIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q20EWBYIG TR requirements.

6.How does Aetrix verify that W25Q20EWBYIG TR is sourced from the original manufacturer or authorized distributors?

All W25Q20EWBYIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q20EWBYIG TR meets industry standards.

7.What is the process for return or replacement of W25Q20EWBYIG TR?

All W25Q20EWBYIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q20EWBYIG TR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The W25Q20EWBYIG TR part is unused and in its original packaging.

Return procedure for W25Q20EWBYIG TR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…