Winbond Electronics Corporation W25Q40BWSVIG TR
- Part No.:
- W25Q40BWSVIG TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
W25Q40BWSVIG TR.pdf
- Description:
- IC FLASH 4MBIT SPI/QUAD 8VSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q40BWSVIG TR from Winbond is a 4M-bit (512KB) 1.8V serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces. It delivers up to 320MHz equivalent data transfer via Quad I/O Fast Read (EBh), features uniform 4KB sector erase, 64KB block erase, and supports execute-in-place (XIP) for code storage in microcontroller boot applications.
For engineers reviewing the W25Q40BWSVIG TR datasheet, W25Q40BWSVIG TR pinout, W25Q40BWSVIG TR application, or W25Q40BWSVIG TR equivalent, key selection criteria include 1.65–1.95V supply compatibility, JEDEC-standard ID support, 40MB/s continuous read rate, hardware /WP and /HOLD control, and non-volatile Quad Enable (QE) bit configuration for Quad SPI mode.
Technical Context
The W25Q40BWSVIG TR implements a SPI-compatible command set with three operational modes: Standard (DI/DO), Dual (IO0/IO1), and Quad (IO0–IO3), where IO2 and IO3 are repurposed from /WP and /HOLD only when QE=1 in Status Register-2. Its architecture includes a 256-byte page buffer, 128 erasable 4KB sectors, and 8 erasable 64KB blocks.
It supports full instruction-level compatibility with JEDEC JESD216, including Manufacturer ID (EFh), Device ID (4013h), and 64-bit unique serial number. Erase/program suspend/resume functionality enables interruptible operations, and security registers (4×256-byte OTP-locked) provide configurable data protection independent of main array access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 M-bit (512 KB), organized as 2,048 × 256-byte pages |
| Supply Voltage | 1.65 V to 1.95 V - enables direct integration with 1.8V logic domains without level shifting |
| Max Clock Frequency | 80 MHz SPI clock - yields 160 MHz (Dual I/O) or 320 MHz (Quad I/O) effective throughput |
| Erase Granularity | 4 KB sector / 32 KB block / 64 KB block / full chip - supports fine-grained firmware update partitioning |
| Write Endurance | 100,000 program/erase cycles per sector - suitable for field-upgradable embedded firmware |
| Data Retention | 20 years at +25°C - meets long-lifecycle industrial and automotive storage requirements |
| Operating Temp | –40°C to +85°C - qualified for extended temperature industrial environments |
| Continuous Read Rate | 40 MB/s - enables efficient XIP execution and rapid code shadowing to RAM |
Pinout & Package
W25Q40BWSVIG TR is packaged in an 8-pin VSOP 150-mil (package code SV), with gull-wing leads, 1.27 mm pitch, and body dimensions of 5.0 × 4.0 × 1.6 mm. Pin 1 is marked by a beveled corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable; high-impedance DO during deselect; required low-to-high transition before new instruction acceptance |
| DO (IO1) | Serial Data Output / Bidirectional I/O1 | Unidirectional output in Standard SPI; bidirectional in Dual/Quad SPI; driven on CLK falling edge |
| /WP (IO2) | Write Protect Input / Bidirectional I/O2 | Hardware write lock for status register; becomes IO2 in Quad SPI when QE=1 |
| GND | Ground Reference | Primary return path for VCC and I/O signals; must be low-impedance for stable SPI timing |
| DI (IO0) | Serial Data Input / Bidirectional I/O0 | Unidirectional input in Standard SPI; bidirectional in Dual/Quad SPI; sampled on CLK rising edge |
| CLK | Serial Clock Input | Synchronous timing reference; supports SPI Modes 0 and 3; max 80 MHz frequency |
| /HOLD (IO3) | Hold Input / Bidirectional I/O3 | Pauses active operation while /CS remains low; becomes IO3 in Quad SPI when QE=1 |
| VCC | Power Supply | 1.65–1.95 V core supply; internal charge pumps generate programming voltages; decoupling capacitor required |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI Enable (QE) | Non-volatile Status Register-2 bit enabling IO2/IO3; required for all Quad I/O instructions (EBh, E7h, etc.) |
| Erase/Program Suspend | 75h/7Ah instructions allow pausing ongoing erase/program to service interrupts, then resuming without data loss |
| 64-bit Unique Serial Number | JEDEC-compliant per-device identifier accessible via 4Bh instruction - enables secure device authentication and traceability |
| Security Registers | 4 × 256-byte OTP-locked regions for storing keys, calibration data, or firmware signatures inaccessible to standard read commands |
| Continuous Read Mode | Wrap-length configurable (8/16/32/64 bytes); as few as 8 clocks overhead per address - essential for deterministic XIP latency |
| Hardware Write Protection | /WP pin + SRP/BP bits enable simultaneous hardware/software locking of 4KB sectors or top/bottom array segments |
Applications
| Boot Code Storage | Firmware Over-the-Air (OTA) |
|---|---|
Use Scenario: Storing primary bootloader and initial firmware image for ARM Cortex-M or RISC-V microcontrollers. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP capability; accessed via Quad SPI at boot time to minimize startup latency. Use Value: 40MB/s continuous read and 8-clock addressing enable sub-100ms firmware load; 4KB sector granularity allows atomic bootloader updates without risking corruption. | Use Scenario: Hosting field-upgradable application firmware in connected IoT gateways or smart meters. IC Role / Device Role / Timing Role: Dual-bank update storage with sector-level erase isolation; used alongside MCU's DMA-driven SPI interface. Use Value: 100,000 erase cycles and 20-year retention ensure >10 years of secure OTA deployments; /HOLD support enables safe interrupt handling during flash writes. |
| Configuration & Calibration Data | Secure Key Storage |
Use Scenario: Retaining device-specific calibration coefficients, network credentials, and user preferences across power cycles. IC Role / Device Role / Timing Role: Parameter storage partitioned into protected 4KB sectors; accessed via Fast Read Dual Output (3Bh) during initialization. Use Value: Hardware /WP + BP bits prevent accidental overwrite; 1.65–1.95V operation ensures compatibility with low-power PMIC rails. | Use Scenario: Isolating cryptographic keys and certificate chains from main firmware in medical or industrial controllers. IC Role / Device Role / Timing Role: Dedicated OTP-locked security registers (LB0–LB3) accessed only via 42h/48h instructions. Use Value: 4×256-byte one-time-programmable regions prevent runtime key exposure; independent lock bits enable per-key revocation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| W25Q40EWXIG TR | Same density and voltage range, but uses USON 2x3-mm package (UX) instead of VSOP (SV); identical pinout and instruction set | Better suited for space-constrained PCBs requiring ultra-small footprint; thermal performance differs due to package construction | Select W25Q40EWXIG TR only if board layout mandates USON 2x3-mm; verify reflow profile compatibility with thinner mold compound. |
| AT25SF041-SSHD-B | 4M-bit, 1.7–2.0V supply; supports DTR (Double Transfer Rate) Quad SPI; lacks 64-bit UID and security registers | Preferred for cost-sensitive consumer designs needing DTR mode; not suitable for secure key storage or device traceability use cases | Choose AT25SF041-SSHD-B when DTR timing margin is critical and security features are unnecessary; confirm /HOLD and /WP behavior matches system control logic. |
Compared with W25Q40BWSVIG TR, W25Q40EWXIG TR offers identical functionality in a smaller USON package but requires different thermal management, while AT25SF041-SSHD-B adds DTR support at the expense of security registers and unique ID - making W25Q40BWSVIG TR optimal for industrial firmware integrity and traceability requirements.
Availability
W25Q40BWSVIG TR is available at Aetrix Electronics and suitable for industrial control systems, automotive infotainment boot storage, and medical device firmware hosting requiring stable component supply, long-term lifecycle assurance, and JEDEC-compliant identification.
Supply support for W25Q40BWSVIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including SPI NOR/NAND flash, RAM, and mobile DRAM.
The W25Q series was designed specifically for embedded systems requiring high-speed, low-voltage, and secure code and data storage - with emphasis on XIP capability, robust write protection, and industrial temperature reliability.
FAQ
What is the operating voltage range for W25Q40BWSVIG TR?
W25Q40BWSVIG TR operates from 1.65 V to 1.95 V. This narrow 1.8V nominal range eliminates the need for external level shifters when interfacing with 1.8V microcontrollers or FPGAs. Operation outside this range may cause undefined behavior or permanent damage. The device includes internal voltage regulation and charge pumps to support programming and erase functions without additional supply rails.
Does W25Q40BWSVIG TR support Quad SPI mode out of the box?
No, W25Q40BWSVIG TR requires explicit configuration to enable Quad SPI mode. The non-volatile Quad Enable (QE) bit in Status Register-2 must be set using the Write Status Register (01h) instruction. Until QE=1, pins /WP and /HOLD remain dedicated to hardware protection functions and cannot serve as IO2/IO3. Default power-on state has QE=0.
How many erase cycles does W25Q40BWSVIG TR guarantee per sector?
W25Q40BWSVIG TR guarantees a minimum of 100,000 program/erase cycles per 4KB sector. This endurance rating applies under specified operating conditions (1.65–1.95V, –40°C to +85°C) and is validated per JEDEC standards. Wear leveling must be implemented in firmware to distribute writes across sectors and achieve full lifecycle potential.
Can W25Q40BWSVIG TR be used for execute-in-place (XIP) applications?
Yes, W25Q40BWSVIG TR supports true XIP via Continuous Read Mode with wrap lengths of 8/16/32/64 bytes and as few as 8 clock cycles of instruction overhead per address. When combined with Fast Read Quad I/O (EBh) at 80 MHz, it delivers up to 40 MB/s sustained throughput - sufficient for real-time code execution in Cortex-M4/M7 and RISC-V cores without local RAM buffering.
What package type does W25Q40BWSVIG TR use?
W25Q40BWSVIG TR uses an 8-pin VSOP 150-mil package (package code SV), with gull-wing leads, 1.27 mm pitch, and body dimensions of 5.0 mm × 4.0 mm × 1.6 mm. This package is pin-compatible with SOIC-8 and supports standard reflow soldering profiles. Top-side marking includes "W25Q40BW" and date code per Winbond specification.
W25Q40BWSVIG TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 80 MHz
- Write Cycle Time - Word, Page:
- 800µs
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSOP
W25Q40BWSVIG TR FAQ
1.How can I place an order for W25Q40BWSVIG TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q40BWSVIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q40BWSVIG TR reliable?
The price and inventory of W25Q40BWSVIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q40BWSVIG TR is usually 5 days.
3.What payment methods are accepted for W25Q40BWSVIG TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q40BWSVIG TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q40BWSVIG TR?
W25Q40BWSVIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q40BWSVIG TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q40BWSVIG TR?
For technical support, including W25Q40BWSVIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q40BWSVIG TR requirements.
6.How does Aetrix verify that W25Q40BWSVIG TR is sourced from the original manufacturer or authorized distributors?
All W25Q40BWSVIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q40BWSVIG TR meets industry standards.
7.What is the process for return or replacement of W25Q40BWSVIG TR?
All W25Q40BWSVIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q40BWSVIG TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q40BWSVIG TR part is unused and in its original packaging.
Return procedure for W25Q40BWSVIG TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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