Winbond Electronics Corporation W25Q40EWBYIG TR
- Part No.:
- W25Q40EWBYIG TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-XFBGA, WLCSP
- Datasheet:
-
W25Q40EWBYIG TR.pdf
- Description:
- IC FLASH 4MBIT SPI/QUAD 8WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:1,308
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q40EWBYIG TR from Winbond is a 4 M-bit (512 KB) serial flash memory IC designed for code storage and XIP (execute-in-place) in space-constrained embedded systems. It operates from 1.65V to 1.95V, supports Dual/Quad SPI and QPI interfaces, delivers up to 104 MHz clock rate (416 MHz equivalent Quad I/O), and features uniform 4 KB sector erase, 100K program-erase cycles, and -40°C to +85°C industrial temperature range.
For engineers reviewing the W25Q40EWBYIG TR datasheet, W25Q40EWBYIG TR pinout, W25Q40EWBYIG TR application, or W25Q40EWBYIG TR equivalent, key selection criteria include voltage compatibility (1.65–1.95 V), Quad SPI enable requirement (QE bit in Status Register-2), hardware write protection via /WP pin, 8-pin USON 2×3 mm package footprint, and JEDEC-compliant SFDP register support for auto-configuration.
Technical Context
The W25Q40EWBYIG TR implements a flexible SPI-compatible command set with three operational modes: Standard SPI (DI/DO), Dual SPI (IO0/IO1), and Quad SPI/QPI (IO0–IO3). Its architecture includes a 256-byte page buffer, 128 uniform 4 KB sectors, and 8 × 64 KB blocks, enabling granular erase control for firmware partitioning and parameter storage.
Functional behavior depends on volatile/non-volatile status register configuration: Quad Enable (QE) must be set non-volatily in Status Register-2 to activate IO2 (/WP) and IO3 (/HOLD); /HOLD and /WP functions are disabled in Quad SPI/QPI mode; and security registers (3 × 256 bytes) support OTP locking for secure boot or calibration data.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 M-bit (512 KB), organized as 2,048 × 256-byte pages |
| Supply Voltage | 1.65 V to 1.95 V - enables direct integration with 1.8 V logic domains without level shifting |
| Max Clock Frequency | 104 MHz SPI clock - yields 416 MB/s effective throughput in Quad I/O Fast Read (EBh) |
| Erase Granularity | Uniform 4 KB sectors (128 total), 32 KB blocks (16), 64 KB blocks (8) - supports fine-grained firmware updates |
| Endurance & Retention | 100,000 program/erase cycles per sector; >20 years data retention at 85°C |
| Operating Temperature | -40°C to +85°C - qualified for industrial-grade operation without derating |
| Interface Modes | Standard/Dual/Quad SPI and QPI - QPI reduces instruction overhead to 2 clocks vs. 8 in SPI |
Pinout & Package
W25Q40EWBYIG TR is packaged in an 8-pad USON 2×3 mm (package code UXIE), with wettable flank side walls for automated optical inspection. Pin 1 is marked by a dot; pin numbering follows standard counter-clockwise orientation from top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable: high = device deselected (high-Z DO, standby current); low = active communication window |
| DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional I/O1 in Dual/Quad SPI/QPI - used for read data and instruction response |
| /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware write lock for status register when QE=0; becomes IO2 in Quad SPI/QPI - requires external pull-up if unused |
| GND | Ground Reference | Signal and power return path - must be low-impedance connection to minimize noise coupling into SPI lines |
| DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional I/O0 in Dual/Quad SPI/QPI - carries instructions, addresses, and program data |
| CLK | Serial Clock Input | Synchronous timing reference - supports Mode 0 and Mode 3; max 104 MHz; edge-triggered for all transfers |
| /HOLD (IO3) | Hold Input / Bidirectional I/O | Pauses ongoing SPI transaction when low (CS must remain low); becomes IO3 in Quad SPI/QPI - not functional during those modes |
| VCC | Power Supply | 1.65–1.95 V core supply - decoupling capacitor (≥1 µF ceramic) required within 5 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Quad Enable (QE) bit | Non-volatile Status Register-2 bit that permanently reassigns /WP and /HOLD to IO2/IO3 - required before any Quad SPI/QPI use |
| Erase/Program Suspend | Allows pausing active erase or program operations to service higher-priority interrupts - resumes from exact byte address |
| 64-bit Unique Serial Number | Factory-programmed, read-only identifier per die - enables secure device authentication and firmware binding |
| SFDP Register | JEDEC-standard 256-byte flash parameter table - allows host bootloader to auto-detect density, timing, and command set without hardcoding |
| Security Registers | Three 256-byte OTP-lockable regions - suitable for storing cryptographic keys, calibration coefficients, or secure boot manifests |
Applications
| IoT Edge Node Firmware Storage | Industrial PLC Boot Memory |
|---|---|
|
Use Scenario: Storing MCU firmware images and OTA update payloads in battery-powered wireless sensors with strict PCB area constraints. IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP capability - eliminates need for external RAM loading during boot. Use Value: 4 KB sector erase enables atomic firmware patching; 1 µA power-down current extends battery life; 1.8 V operation matches SoC I/O voltage. |
Use Scenario: Holding real-time OS kernel, configuration tables, and safety-critical ladder logic in programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Industrial-grade boot memory interfacing directly with ARM Cortex-M7 or RISC-V application processors via Quad SPI. Use Value: -40°C to +85°C rating ensures reliability across thermal cycling; 100K endurance supports frequent field firmware upgrades. |
| Medical Diagnostic Device Parameter Storage | Automotive ADAS Camera Module Code Storage |
|
Use Scenario: Retaining calibrated sensor offsets, user preferences, and audit logs in portable ultrasound or ECG units requiring long-term data integrity. IC Role / Device Role / Timing Role: Secure parameter archive with hardware write protection - /WP pin and BP bits prevent accidental overwrites during field servicing. Use Value: OTP-locked security registers store calibration keys; 20-year data retention meets medical device regulatory requirements. |
Use Scenario: Hosting camera ISP firmware and neural network inference models in automotive surround-view systems where compact packaging is critical. IC Role / Device Role / Timing Role: High-speed code execution source - Quad I/O Fast Read (EBh) delivers >50 MB/s sustained throughput for real-time image processing. Use Value: USON 2×3 mm footprint saves board space vs. SOIC; QPI mode reduces CPU instruction overhead during boot sequence. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L4006EM1I-12G | 4 M-bit, 1.65–2.0 V, 80 MHz max clock, SOIC-8 only - no USON or WLCSP; lacks QPI and SFDP support | Lower throughput limits suitability for XIP in performance-sensitive designs; no unique ID or security registers | Select when cost sensitivity outweighs need for Quad I/O speed or advanced security features. |
| AT25SF041-SSHD-B | 4 M-bit, 1.7–2.0 V, 104 MHz, USON-8 available - supports Dual/Quad SPI but no QPI; includes 64-bit UID and basic security registers | Missing QPI mode and SFDP register - requires manual configuration; slightly narrower voltage range than W25Q40EWBYIG TR | Choose when QPI is unnecessary and legacy SPI controller compatibility is prioritized over future-proofing. |
Compared with MX25L4006EM1I-12G and AT25SF041-SSHD-B, the W25Q40EWBYIG TR uniquely combines QPI mode for reduced instruction latency, JEDEC SFDP for plug-and-play initialization, and OTP-secured registers - making it optimal for next-generation embedded systems requiring both speed and security.
Availability
W25Q40EWBYIG TR is available at Aetrix Electronics and suitable for IoT edge node firmware storage, industrial PLC boot memory, and medical diagnostic device parameter storage requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.
Supply support for W25Q40EWBYIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial flash, PSRAM, and mobile DRAM, serving industrial, automotive, and consumer markets since 1987.
The W25Q series targets high-performance embedded applications demanding fast XIP, low-voltage operation, and robust data integrity - specifically engineered for code storage, firmware updates, and secure parameter retention in resource-constrained systems.
FAQ
What is the package type and dimensions of the W25Q40EWBYIG TR?
The W25Q40EWBYIG TR uses an 8-pad USON (Ultra Thin Small Outline No-lead) package measuring 2 mm × 3 mm with 0.5 mm pitch and wettable flank side walls. This compact footprint supports automated optical inspection and is ideal for space-constrained PCB layouts in portable and industrial electronics.
Does the W25Q40EWBYIG TR support Quad SPI and QPI modes out of the box?
No - the W25Q40EWBYIG TR defaults to Standard SPI mode after power-up. To enable Quad SPI or QPI, the non-volatile Quad Enable (QE) bit in Status Register-2 must first be set using the Write Status Register-2 (31h) instruction. Only then do /WP and /HOLD become IO2 and IO3 for full Quad I/O functionality.
How does hardware write protection work on the W25Q40EWBYIG TR?
Hardware write protection on the W25Q40EWBYIG TR is implemented via the /WP pin, which - when held low - prevents writes to the status register regardless of software commands. This works in conjunction with block protect (BP) bits and status register protect (SRP) settings to lock specific memory regions, ensuring critical firmware or calibration data remains unaltered during system operation.
What is the purpose of the SFDP register in the W25Q40EWBYIG TR?
The SFDP (Serial Flash Discoverable Parameters) register in the W25Q40EWBYIG TR is a JEDEC-standard 256-byte table that provides host processors with machine-readable information about memory density, timing parameters, erase block sizes, and supported instruction sets. This enables automatic, vendor-agnostic flash initialization without hardcoded configuration tables.
Can the W25Q40EWBYIG TR be used for secure boot applications?
Yes - the W25Q40EWBYIG TR supports secure boot through its 64-bit unique serial number, three 256-byte security registers with OTP locking capability, and hardware write protection. These features allow cryptographic keys, signature hashes, and immutable boot manifests to be stored and protected against tampering or unauthorized modification.
W25Q40EWBYIG TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-XFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 30µs, 800µs
- Access Time:
- 6 ns
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WLCSP (1.34x1.63)
W25Q40EWBYIG TR FAQ
1.How can I place an order for W25Q40EWBYIG TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q40EWBYIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q40EWBYIG TR reliable?
The price and inventory of W25Q40EWBYIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q40EWBYIG TR is usually 5 days.
3.What payment methods are accepted for W25Q40EWBYIG TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q40EWBYIG TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q40EWBYIG TR?
W25Q40EWBYIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q40EWBYIG TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q40EWBYIG TR?
For technical support, including W25Q40EWBYIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q40EWBYIG TR requirements.
6.How does Aetrix verify that W25Q40EWBYIG TR is sourced from the original manufacturer or authorized distributors?
All W25Q40EWBYIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q40EWBYIG TR meets industry standards.
7.What is the process for return or replacement of W25Q40EWBYIG TR?
All W25Q40EWBYIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q40EWBYIG TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q40EWBYIG TR part is unused and in its original packaging.
Return procedure for W25Q40EWBYIG TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q40EWBYIG TR Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

