Winbond Electronics Corporation W25Q80BLSVIG
- Part No.:
- W25Q80BLSVIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
W25Q80BLSVIG.pdf
- Description:
- IC FLASH 8MBIT SPI/QUAD 8VSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,097
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q80BLSVIG from Winbond is an 8 M-bit (1 MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with up to 50 MHz clock frequency, 4 KB uniform sector erase granularity, and true execute-in-place (XIP) capability for embedded code storage and execution. It operates from a single 2.3–3.6 V supply, draws 4 mA active current and <1 µA in power-down mode, and is rated for -40°C to +85°C industrial temperature range.
For engineers reviewing the W25Q80BLSVIG datasheet, W25Q80BLSVIG pinout, W25Q80BLSVIG application, or W25Q80BLSVIG equivalent, key selection considerations include Quad SPI enable (QE bit), hardware write protection via /WP and /HOLD pins, 4 KB sector flexibility for firmware partitioning, JEDEC ID and SFDP register support for auto-configuration, and compatibility with XIP-capable microcontrollers in space-constrained IoT and industrial control designs.
Technical Context
The W25Q80BLSVIG implements a flexible SPI command architecture supporting three operational modes: Standard SPI (DI/DO), Dual SPI (IO0/IO1), and Quad SPI (IO0–IO3), where IO2 and IO3 are remapped from /WP and /HOLD only when the non-volatile Quad Enable (QE) bit in Status Register-2 is set. Its internal block diagram includes a 256-byte page buffer, sector/block erase logic, and dedicated security registers with OTP locks.
It features dual status registers (SR-1 and SR-2) with programmable protection bits (BP2–BP0, TB, SEC, CMP, SRP0/SRP1), erase/program suspend/resume functionality, and a 64-bit unique serial number. The device supports continuous read mode with as few as 8 clocks overhead per 24-bit address access, enabling efficient XIP operation without external buffering.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 8 M-bit (1,048,576 bytes), organized as 4,096 × 256-byte pages |
| SPI Interface Modes | Standard (4-wire), Dual I/O (5-wire), Quad I/O (6-wire); QE bit required for Quad mode |
| Max Clock Frequency | 50 MHz standard/Dual/Quad SPI; enables 100 MHz (Dual) or 200 MHz (Quad) effective throughput |
| Erase Granularity | Uniform 4 KB sectors (256 total), 32 KB blocks (32 total), 64 KB blocks (16 total), full chip erase |
| Write/Erase Endurance | ≥100,000 program/erase cycles per sector; ≥20 years data retention at +85°C |
| Supply Voltage | 2.3 V to 3.6 V single supply; compatible with 2.5 V and 3.3 V system rails |
| Operating Temperature | -40°C to +85°C industrial grade; validated across full voltage and timing margins |
Pinout & Package
W25Q80BLSVIG is packaged in an 8-pin SOIC 208-mil (package code SS), with lead-free, RoHS-compliant construction and surface-mount footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO output and standby current when high |
| 2 DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad SPI |
| 3 /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware write lock for status register; becomes IO2 in Quad SPI when QE=1 |
| 4 GND | Ground Reference | Primary return path for VCC and all I/O signals; requires low-impedance PCB connection |
| 5 DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad SPI |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference for all SPI operations; supports Mode 0 and Mode 3 |
| 7 /HOLD (IO3) | Hold Input / Bidirectional I/O | Pauses ongoing SPI transfer; becomes IO3 in Quad SPI when QE=1 |
| 8 VCC | Power Supply | 2.3–3.6 V core and I/O supply; decoupling capacitor required per datasheet layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI with QE bit | Enables 200 MHz effective throughput and XIP-ready memory mapping via IO0–IO3 remapping |
| Continuous Read Mode | Reduces instruction overhead to ≤8 clocks per 24-bit address, enabling deterministic XIP latency |
| 4 KB uniform sector architecture | Allows fine-grained firmware updates and parameter storage without erasing unrelated code regions |
| Dual status registers with SRP/BP bits | Supports hardware/software hybrid write protection down to individual 4 KB sectors |
| 64-bit unique serial number | Enables device-level traceability and secure boot key binding in certified embedded systems |
| SFDP register compliance | Permits automatic configuration of timing, voltage, and feature sets by host bootloader without hardcoding |
Applications
| Firmware Storage for MCU Boot | IoT Edge Device Code Execution |
|---|---|
|
Use Scenario: Storing bootloader and application firmware for ARM Cortex-M microcontrollers with XIP-capable QSPI peripherals. IC Role / Device Role / Timing Role: Primary non-volatile code storage with direct bus execution; provides deterministic 50 MHz SPI timing and sector-level update isolation. Use Value: Eliminates RAM copy overhead during boot, reduces BOM cost vs. parallel flash, and enables over-the-air firmware patching to specific 4 KB sectors. |
Use Scenario: Hosting sensor fusion algorithms and connectivity stack (Wi-Fi/BLE) in battery-powered smart sensors. IC Role / Device Role / Timing Role: Low-power code and configuration storage; leverages <1 µA power-down current and hardware /WP protection during sleep. Use Value: Extends battery life via ultra-low quiescent current, prevents accidental corruption during brown-out events using /WP and SRP bits. |
| Industrial HMI Display Memory | Medical Diagnostic Equipment Data Log |
|
Use Scenario: Storing GUI assets, fonts, and localized language strings for touch-based human-machine interface panels. IC Role / Device Role / Timing Role: High-bandwidth asset delivery via Quad SPI Fast Read (EBh); supports burst reads with wrap for seamless image streaming. Use Value: Achieves >25 MB/s sustained read throughput, enabling smooth 60 fps UI rendering without frame drops or external cache. |
Use Scenario: Recording time-stamped physiological waveforms and calibration metadata in portable ECG or EEG devices. IC Role / Device Role / Timing Role: Reliable parameter and event log storage with 100,000+ erase cycles and 20-year retention at elevated ambient temperatures. Use Value: Guarantees long-term integrity of clinical data across device lifecycle; supports sector-locking to preserve calibration records during field updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q80DVSSIG | Same density and pinout; supports higher 104 MHz Quad SPI (DTR mode) and extended -40°C to +105°C temp range | Required for automotive AEC-Q100 Grade 3 or high-temp industrial environments | Select W25Q80DVSSIG if operating above +85°C or requiring DTR protocol support; otherwise W25Q80BLSVIG offers cost-optimized industrial-grade performance. |
| Micron MT25QL08ABB8E12-0SIT | 8 M-bit, SOIC-8, 133 MHz Quad SPI; includes built-in hardware reset and enhanced SFDP v1.6 compliance | Better suited for complex bootloaders requiring vendor-agnostic SFDP parsing and robust power-on reset behavior | Choose MT25QL08ABB8E12-0SIT when interoperability with multi-vendor toolchains or guaranteed POR sequencing is critical; W25Q80BLSVIG remains optimal for cost-sensitive, fixed-platform designs. |
Compared with W25Q80DVSSIG and MT25QL08ABB8E12-0SIT, the W25Q80BLSVIG delivers proven industrial reliability at lower unit cost, with sufficient 50 MHz Quad SPI bandwidth and 4 KB sector granularity for most MCU-based embedded applications-making it the preferred choice where extended temperature or advanced SFDP features are not required.
Availability
W25Q80BLSVIG is available at Aetrix Electronics and suitable for firmware storage, IoT edge device code execution, and industrial HMI display memory requiring stable component supply, long-lifecycle support, and RoHS-compliant sourcing.
Supply support for W25Q80BLSVIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash, RAM, and mobile DRAM, serving industrial, automotive, and consumer markets since 1987.
The W25Q series was designed specifically for embedded systems requiring reliable, low-pin-count, high-performance code storage with XIP capability-targeting microcontroller-based applications where space, power, and interface simplicity are critical constraints.
FAQ
What is the maximum SPI clock frequency supported by the W25Q80BLSVIG?
The W25Q80BLSVIG supports up to 50 MHz for Standard, Dual, and Quad SPI operations. This enables 100 MHz effective throughput in Dual I/O mode and 200 MHz in Quad I/O mode when using Fast Read Dual I/O (BBh) or Fast Read Quad I/O (EBh) instructions. Timing compliance is verified across the full -40°C to +85°C temperature range and 2.3–3.6 V supply voltage window specified in the datasheet.
Does the W25Q80BLSVIG support execute-in-place (XIP) operation?
Yes, the W25Q80BLSVIG supports true XIP via its Continuous Read Mode, which reduces instruction overhead to as few as 8 clock cycles per 24-bit address access. When paired with a microcontroller's QSPI peripheral configured for Quad I/O, the W25Q80BLSVIG allows direct code execution from flash without copying to RAM-reducing boot time and SRAM usage in resource-constrained designs.
How is hardware write protection implemented on the W25Q80BLSVIG?
The W25Q80BLSVIG implements hardware write protection using the /WP (pin 3) signal, which-when held low-prevents writes to the status register. This works in conjunction with software-configurable Block Protect (BP2–BP0), Top/Bottom (TB), and Status Register Protect (SRP0/SRP1) bits to lock sectors as small as 4 KB. Note that /WP is disabled during Quad SPI operation when the QE bit is set, as pin 3 becomes IO2.
What package type does the W25Q80BLSVIG use, and is it RoHS-compliant?
The W25Q80BLSVIG uses an 8-pin SOIC 208-mil package (package code SS), with gull-wing leads and Pb-free, RoHS-compliant finish. Its dimensions (8.89 mm × 3.94 mm × 1.78 mm) and thermal characteristics are fully documented in Section 8.3 of the Winbond datasheet, and it is qualified for reflow soldering per J-STD-020 standards.
Can the W25Q80BLSVIG be used in automotive applications?
The W25Q80BLSVIG is rated for industrial temperature (-40°C to +85°C) and is not AEC-Q100 qualified. For automotive applications requiring Grade 2 (-40°C to +105°C) or Grade 3 (-40°C to +125°C) qualification, Winbond recommends the W25Q80DVxxIG series instead. The W25Q80BLSVIG remains suitable for under-dash infotainment modules or gateway ECUs operating within its specified temperature envelope.
W25Q80BLSVIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 8Mbit
- Memory Organization:
- 1M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 80 MHz
- Write Cycle Time - Word, Page:
- 800µs
- Access Time:
- -
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSOP
W25Q80BLSVIG FAQ
1.How can I place an order for W25Q80BLSVIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q80BLSVIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q80BLSVIG reliable?
The price and inventory of W25Q80BLSVIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q80BLSVIG is usually 5 days.
3.What payment methods are accepted for W25Q80BLSVIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q80BLSVIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q80BLSVIG?
W25Q80BLSVIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q80BLSVIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q80BLSVIG?
For technical support, including W25Q80BLSVIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q80BLSVIG requirements.
6.How does Aetrix verify that W25Q80BLSVIG is sourced from the original manufacturer or authorized distributors?
All W25Q80BLSVIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q80BLSVIG meets industry standards.
7.What is the process for return or replacement of W25Q80BLSVIG?
All W25Q80BLSVIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q80BLSVIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q80BLSVIG part is unused and in its original packaging.
Return procedure for W25Q80BLSVIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q80BLSVIG Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

