Winbond Electronics Corporation W25Q80BVSSIG
- Part No.:
- W25Q80BVSSIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
W25Q80BVSSIG.pdf
- Description:
- IC FLASH 8MBIT SPI/QUAD 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,642
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Product details
Overview
W25Q80BVSSIG from Winbond is an 8 M-bit (1 MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces. It features 4,096 × 256-byte pages, 4 KB uniform sectors, 104 MHz max clock frequency, and operates from 2.5 V to 3.6 V with 4 mA active and <1 µA power-down current. It enables XIP (execute-in-place) code execution in microcontroller boot loaders and firmware storage applications.
For engineers reviewing the W25Q80BVSSIG datasheet, W25Q80BVSSIG pinout, W25Q80BVSSIG application, or W25Q80BVSSIG equivalent, key selection criteria include Quad SPI enable (QE bit), sector/block erase granularity (4/32/64 KB), hardware write protection via /WP and /HOLD pins, and JEDEC-compliant identification including 64-bit unique serial number.
Technical Context
The W25Q80BVSSIG implements a SPI command set compliant with Mode 0 and Mode 3 clock polarity/idle states, with dedicated instruction decoding for standard (03h/02h), dual (3Bh/BBh), and quad (6Bh/EBh/E7h) read/write operations. Its internal architecture includes a 256-byte page buffer, status register-1 and -2 with non-volatile QE bit, and SFDP register for discoverable parameters.
Quad SPI operation requires explicit setting of the Quad Enable (QE) bit in Status Register-2; when enabled, /WP and /HOLD become IO2 and IO3, disabling their hardware protection functions. Erase/program suspend/resume (75h/7Ah) and security registers (3×256-byte OTP-locked) support robust firmware update sequencing and secure parameter storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 8 M-bit (1,048,576 bytes), organized as 4,096 pages × 256 bytes |
| Sector Size | Uniform 4 KB sectors (256 total); supports 32 KB and 64 KB block erase |
| Max Clock Frequency | 104 MHz for standard/dual/quad SPI; enables 416 MHz equivalent quad I/O throughput |
| Supply Voltage | 2.5 V to 3.6 V - compatible with 3.3 V logic systems without level shifting |
| Active & Power-down Current | 4 mA typical active current; <1 µA deep power-down current for battery-sensitive designs |
| Data Retention | 20+ years at +25°C - validated for long-life industrial and automotive firmware storage |
| Erase/Program Cycles | 100,000 minimum cycles per sector - sufficient for field firmware updates over product lifetime |
Pinout & Package
W25Q80BVSSIG is supplied in an 8-pin SOIC 208-mil package (package code SS), with lead-free, RoHS-compliant finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; must transition high→low after power-up before first instruction |
| 2 DO (IO1) | Data Output / I/O1 | Unidirectional output in standard SPI; bidirectional I/O in dual/quad modes |
| 3 /WP (IO2) | Write Protect Input / I/O2 | Hardware lock for status register when QE=0; becomes IO2 in quad mode (QE=1) |
| 4 GND | Ground Reference | System common return; decoupling capacitor required near VCC pin |
| 5 DI (IO0) | Data Input / I/O0 | Unidirectional input in standard SPI; bidirectional I/O in dual/quad modes |
| 6 CLK | Serial Clock Input | Edge-triggered timing source; supports Mode 0 and Mode 3 SPI clock polarity |
| 7 /HOLD (IO3) | Hold Input / I/O3 | Pauses ongoing SPI transaction when low; becomes IO3 in quad mode (QE=1) |
| 8 VCC | Power Supply | 2.5–3.6 V supply; requires local 0.1 µF ceramic decoupling capacitor |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI Enable (QE bit) | Non-volatile Status Register-2 bit enabling 4-line I/O for 416 MHz equivalent throughput |
| Continuous Read Mode | As few as 8 clocks overhead per 24-bit address; enables true XIP execution without external RAM buffering |
| Flexible Erase Granularity | Independent 4 KB sector, 32 KB block, 64 KB block, and full-chip erase - ideal for parameter + firmware partitioning |
| Security Registers | Three 256-byte OTP-lockable registers for secure keys, calibration data, or device-specific credentials |
| 64-bit Unique Serial Number | Jedec-standard unique ID per unit - enables secure device authentication and traceability in production |
Applications
| Boot Code Storage | Firmware Update Storage |
|---|---|
Use Scenario: Storing primary bootloader and initial firmware image for ARM Cortex-M or RISC-V microcontrollers during cold start. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Quad SPI interface enabling direct CPU execution without RAM copy. Use Value: Reduces BOM cost and PCB footprint by eliminating external parallel flash or SRAM; supports deterministic boot timing via 104 MHz clock. | Use Scenario: Holding signed firmware update images in IoT edge nodes prior to authenticated installation. IC Role / Device Role / Timing Role: Secure, field-upgradable storage with OTP-locked security registers for signature verification keys. Use Value: Enables safe over-the-air (OTA) updates using 100,000-cycle endurance and hardware write protection against corruption. |
| Parameter & Calibration Data | Human-Machine Interface (HMI) Assets |
Use Scenario: Retaining factory-calibrated sensor offsets, motor tuning coefficients, and user preferences in industrial PLCs. IC Role / Device Role / Timing Role: Reliable, sector-level erasable NVM for infrequently modified but mission-critical configuration data. Use Value: 4 KB sector granularity allows independent update of calibration tables without disturbing firmware code regions. | Use Scenario: Hosting bitmap fonts, icon sets, and UI layout metadata for embedded LCD touchscreens in medical devices. IC Role / Device Role / Timing Role: High-bandwidth asset repository accessed via continuous-read Quad SPI for smooth GUI rendering. Use Value: 50 MB/s sustained transfer rate eliminates UI stutter during graphic load; 20-year data retention ensures display integrity over device lifetime. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L8006EM1I-12G | 8 M-bit, 104 MHz max clock, SOIC-8 208-mil, but lacks Quad Enable bit and SFDP register | No native Quad SPI support; requires software-emulated dual-I/O only; no discoverable parameter table | Select when Quad SPI is unnecessary and legacy SPI controller compatibility is prioritized over bandwidth |
| S25FL008KAGMFI011 | 8 M-bit, 80 MHz max clock, SOIC-8 208-mil, includes Quad Enable and SFDP, but no OTP security registers | Lacks 3×256-byte OTP-locked security registers; supports only volatile QE configuration | Select when secure key storage is handled externally, and lower 80 MHz clock meets system timing budgets |
Compared with MX25L8006EM1I-12G and S25FL008KAGMFI011, the W25Q80BVSSIG delivers higher throughput (104 MHz vs. 80 MHz), integrated SFDP for automatic configuration, and hardware-enforced OTP security - making it optimal for XIP-capable, updatable, and security-aware embedded systems.
Availability
W25Q80BVSSIG is available at Aetrix Electronics and suitable for boot loader storage, firmware update staging, and parameter retention requiring stable component supply across industrial control, medical instrumentation, and connected consumer electronics.
Supply support for W25Q80BVSSIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including serial flash, PSRAM, and code storage ICs for embedded systems.
The W25Q series targets high-performance, space-constrained applications requiring reliable code execution, secure firmware updates, and flexible erase architecture - especially in microcontroller-based platforms where SPI resource efficiency is critical.
FAQ
What is the maximum supported SPI clock frequency for W25Q80BVSSIG in Quad I/O mode?
The W25Q80BVSSIG supports up to 104 MHz on the SPI clock (CLK) pin in Quad I/O mode. When combined with four data lines (IO0–IO3), this yields an effective data transfer rate of 416 MHz (104 MHz × 4), enabling 50 MB/s continuous read throughput. This specification is validated under standard operating conditions (2.5–3.6 V, –40°C to +85°C) and requires the Quad Enable (QE) bit in Status Register-2 to be set.
Does W25Q80BVSSIG support execute-in-place (XIP) operation, and what is required to enable it?
Yes, W25Q80BVSSIG supports true XIP operation via its Continuous Read Mode, which reduces instruction overhead to as few as 8 clock cycles per 24-bit address. To enable XIP, the host MCU must issue Fast Read Quad I/O (EBh) or Word Read Quad I/O (E7h) instructions and ensure the Quad Enable (QE) bit in Status Register-2 is set. The device's 104 MHz clock and uniform 4 KB sectors further optimize deterministic code fetch latency.
How does hardware write protection work on W25Q80BVSSIG, and is it available in Quad SPI mode?
Hardware write protection on W25Q80BVSSIG is implemented via the /WP (pin 3) signal, which disables writes to the status register when held low - but only when the Quad Enable (QE) bit is cleared (QE = 0). When QE = 1 for Quad SPI operation, /WP becomes IO2 and hardware write protection is disabled. Software-based protection via Block Protect (BP2–BP0) and Status Register Protect (SRP0/SRP1) bits remains fully functional regardless of QE state.
What package type does W25Q80BVSSIG use, and is it RoHS-compliant?
W25Q80BVSSIG uses an 8-pin SOIC package with 208-mil body width (package code SS), featuring gull-wing leads and a matte tin finish. It is fully RoHS-compliant and lead-free, meeting JEDEC J-STD-020 moisture sensitivity level 3 (MSL3) requirements. The package is pin-compatible with other W25Q80BV variants in SOIC-8 208-mil form factor.
Can W25Q80BVSSIG store a unique identifier per unit, and how is it accessed?
Yes, each W25Q80BVSSIG unit contains a factory-programmed, unalterable 64-bit unique serial number. It is accessed via the Read Unique ID Number instruction (4Bh), which returns the ID across eight consecutive bytes starting at address 000000h. This identifier supports device authentication, anti-cloning, and production traceability without requiring external EEPROM or secure elements.
W25Q80BVSSIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 8Mbit
- Memory Organization:
- 1M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
W25Q80BVSSIG FAQ
1.How can I place an order for W25Q80BVSSIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q80BVSSIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q80BVSSIG reliable?
The price and inventory of W25Q80BVSSIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q80BVSSIG is usually 5 days.
3.What payment methods are accepted for W25Q80BVSSIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q80BVSSIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q80BVSSIG?
W25Q80BVSSIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q80BVSSIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q80BVSSIG?
For technical support, including W25Q80BVSSIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q80BVSSIG requirements.
6.How does Aetrix verify that W25Q80BVSSIG is sourced from the original manufacturer or authorized distributors?
All W25Q80BVSSIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q80BVSSIG meets industry standards.
7.What is the process for return or replacement of W25Q80BVSSIG?
All W25Q80BVSSIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q80BVSSIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q80BVSSIG part is unused and in its original packaging.
Return procedure for W25Q80BVSSIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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