Winbond Electronics Corporation W25Q80BWZPIG
- Part No.:
- W25Q80BWZPIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q80BWZPIG.pdf
- Description:
- IC FLASH 8MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:

- Shipping:

Inventory:4,653
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Product details
Overview
W25Q80BWZPIG from Winbond is an 8 M-bit (1 MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with 1.65–1.95 V single-supply operation, 80 MHz max clock frequency, and 4 KB uniform sector architecture. It delivers up to 40 MB/s continuous read throughput via Quad I/O Fast Read (EBh), enabling execute-in-place (XIP) in resource-constrained embedded systems.
For engineers reviewing the W25Q80BWZPIG datasheet, W25Q80BWZPIG pinout, W25Q80BWZPIG application, or W25Q80BWZPIG equivalent, this page provides verified pin functions, real-world timing behavior, XIP-capable read modes, hardware write protection via /WP and /HOLD, and validated alternatives for code storage and firmware update use cases.
Technical Context
The W25Q80BWZPIG implements a SPI command set compliant with JEDEC JESD216, supports Mode 0 and Mode 3 clock polarity, and requires non-volatile Quad Enable (QE) bit setting in Status Register-2 to activate IO2 (/WP) and IO3 (/HOLD) for Quad SPI operation. Its internal 256-byte page buffer enables byte-aligned programming up to 256 bytes per cycle.
It features dual-level write protection: hardware-based via active-low /WP pin (disabled during Quad mode), and software-configurable via Status Register BP2–BP0, TB, SEC, and CMP bits. Erase granularity includes 4 KB sectors (256 total), 32 KB blocks (16), and 64 KB blocks (8), with chip erase support (C7h/60h).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 8 M-bit (1,048,576 bytes), organized as 4,096 × 256-byte programmable pages |
| Supply Voltage | 1.65 V to 1.95 V - enables direct integration with 1.8 V logic domains without level shifting |
| Max Clock Frequency | 80 MHz - supports 160 MHz effective Dual I/O and 320 MHz effective Quad I/O data rates |
| Erase Granularity | 4 KB sectors (256 units), 32 KB blocks (16), 64 KB blocks (8) - allows fine-grained firmware partitioning |
| Program/Erase Endurance | 100,000 cycles - ensures reliability in frequent OTA update or logging applications |
| Data Retention | 20 years at +25°C - meets long-lifecycle industrial and automotive control requirements |
| Operating Temperature | −40°C to +85°C - qualified for extended-temperature embedded deployment |
| Power Consumption | 4 mA active current, <1 µA power-down - critical for battery-backed or ultra-low-power IoT nodes |
Pinout & Package
W25Q80BWZPIG uses an 8-pin WSON 6×5-mm package (package code ZP), with exposed pad for thermal dissipation and space-constrained PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; must transition high→low after power-up before first instruction; controls DO high-impedance state |
| 2 DO (IO1) | Data Output / Bidirectional I/O1 | Unidirectional output in Standard SPI; bidirectional in Dual/Quad SPI; used for status/data reads on falling CLK edge |
| 3 /WP (IO2) | Write Protect Input / Bidirectional I/O2 | Hardware write lock for Status Register when QE=0; repurposed as IO2 in Quad mode (QE=1) |
| 4 GND | Ground Reference | Primary return path for VCC and I/O signals; requires low-impedance connection to minimize noise coupling |
| 5 DI (IO0) | Data Input / Bidirectional I/O0 | Unidirectional input in Standard SPI; bidirectional in Dual/Quad SPI; accepts instructions/addresses on rising CLK edge |
| 6 CLK | Serial Clock Input | Master-generated timing signal; supports Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1) |
| 7 /HOLD (IO3) | Hold Input / Bidirectional I/O3 | Pauses ongoing SPI transaction when active-low; disabled in Quad mode (QE=1); requires /CS low to function |
| 8 VCC | Power Supply | 1.65–1.95 V supply; must exceed VWI threshold before operations enabled; internal reset holds until stable |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | Enables true XIP with ≤8-clock instruction overhead per 24-bit address; eliminates latency penalties in boot code execution |
| Quad SPI Support | Requires QE bit set; unlocks 320 MHz effective bandwidth using IO0–IO3 - outperforms parallel Flash in density-normalized throughput |
| Flexible Protection Scheme | Combines hardware /WP pin (active-low, disabled in Quad mode) and software-configurable BP/TB/SEC bits for sector- or array-level lockdown |
| Security Registers | Four 256-byte OTP-locked security registers - suitable for storing cryptographic keys or calibration data immune to field reprogramming |
| Unique Serial ID | 64-bit factory-programmed identifier - enables device authentication, traceability, and secure provisioning in production |
| Erase/Program Suspend | 75h/7Ah instructions allow pausing long erase/program cycles to service time-critical interrupts - essential for real-time firmware updates |
Applications
| IoT Edge Node Firmware Storage | Industrial PLC Boot Memory |
|---|---|
|
Use Scenario: Storing MCU boot firmware and field-upgradable application binaries in battery-powered sensor gateways with limited PCB area. IC Role / Device Role / Timing Role: Primary non-volatile code storage accessed via Quad SPI XIP during cold start and OTA update sequences. Use Value: 40 MB/s read speed and 4 KB sector erase enable fast boot (<50 ms) and atomic firmware patching without full chip erase. |
Use Scenario: Holding safety-critical ladder logic and configuration data in modular automation controllers requiring certified data integrity. IC Role / Device Role / Timing Role: Trusted configuration store with hardware write protection and 20-year retention for deterministic startup behavior. Use Value: /WP pin + BP bits prevent accidental overwrite during EMI-rich factory environments; unique ID enables audit-trail firmware versioning. |
| Automotive Infotainment UI Assets | Medical Device Parameter Calibration |
|
Use Scenario: Hosting compressed GUI assets, fonts, and audio prompts in head-unit displays where thermal and space constraints limit package options. IC Role / Device Role / Timing Role: High-bandwidth asset fetch engine using Fast Read Quad I/O (EBh) to feed display controller DMA buffers. Use Value: WSON 6×5-mm footprint fits tight layout zones; −40°C to +85°C rating ensures reliability across vehicle cabin temperature swings. |
Use Scenario: Storing calibrated sensor offsets, patient-specific therapy profiles, and regulatory audit logs in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure parameter vault leveraging OTP security registers and 64-bit unique ID for HIPAA-compliant traceability. Use Value: Four 256-byte OTP-locked regions prevent post-deployment tampering; 100K-cycle endurance supports lifetime recalibration events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L8006EM1I-12G | Same 8 M-bit density, 1.65–1.95 V, SOIC-8 package; supports only Standard/Dual SPI (no Quad I/O) | Lacks Quad SPI interface and Continuous Read Mode - limits XIP performance and increases boot latency | Select when Quad bandwidth is unnecessary and legacy SPI controller compatibility is prioritized over throughput |
| S25FL008KAGMFI010 | 8 M-bit, 1.7–2.0 V, supports Quad SPI and XIP; includes built-in ECC and sector protection lock bits | Offers stronger data integrity via on-die ECC but consumes more power (6 mA active) and lacks OTP security registers | Prefer for safety-critical systems needing error correction, but avoid if ultra-low power (<1 µA sleep) or key storage is required |
Compared with W25Q80BWZPIG, MX25L8006EM1I-12G trades Quad I/O bandwidth for broader controller compatibility, while S25FL008KAGMFI010 adds ECC at the cost of higher active current and no OTP security - making W25Q80BWZPIG optimal for balanced XIP performance, low-power operation, and secure key storage.
Availability
W25Q80BWZPIG is available at Aetrix Electronics and suitable for IoT edge node firmware storage, industrial PLC boot memory, automotive infotainment UI assets, medical device parameter calibration, and other applications requiring stable component supply, guaranteed long-term sourcing, and consistent parametric performance across production batches.
Supply support for W25Q80BWZPIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash, RAM, and mobile DRAM, serving industrial, automotive, and consumer markets since 1987.
The W25Q series targets embedded systems needing high-speed, low-voltage, and space-efficient code storage - designed specifically for XIP-capable microcontrollers, real-time boot loaders, and firmware update architectures.
FAQ
What is the maximum supported SPI clock frequency for W25Q80BWZPIG in Quad I/O mode?
The W25Q80BWZPIG supports up to 80 MHz SPI clock frequency in Quad I/O mode. When combined with quad-line data transfer, this yields an effective throughput of 320 MHz (80 MHz × 4), as confirmed by Fast Read Quad I/O (EBh) timing specifications in the official datasheet. This enables sub-50 ms firmware load times for typical boot images.
Does W25Q80BWZPIG support execute-in-place (XIP) operation, and what conditions are required?
Yes, W25Q80BWZPIG supports true XIP via its Continuous Read Mode, which reduces instruction overhead to as few as 8 clocks per 24-bit address. To enable XIP, the host controller must issue Set Burst with Wrap (77h) and configure the device for Quad I/O mode by setting the Quad Enable (QE) bit in Status Register-2 - both verified in Section 7.2.18 and 7.1.10 of the datasheet.
How does hardware write protection work on W25Q80BWZPIG, and is it available in all SPI modes?
Hardware write protection on W25Q80BWZPIG is implemented via the active-low /WP pin, which locks the Status Register when asserted. However, this function is disabled in Quad SPI mode because the /WP pin is repurposed as IO2 once the QE bit is set. Therefore, /WP protection is only active in Standard and Dual SPI configurations - a design constraint explicitly documented in Sections 4.3 and 6.1.3.
What package type does W25Q80BWZPIG use, and how is it identified by the suffix "ZPIG"?
W25Q80BWZPIG uses the 8-pad WSON 6×5-mm package with exposed thermal pad (package code ZP). The "ZPIG" suffix decodes as: Z = WSON, P = 6×5-mm body, I = Industrial temperature range (−40°C to +85°C), G = RoHS-compliant, lead-free, halogen-free finish - per Winbond's official ordering information table (Section 10.1).
Can W25Q80BWZPIG suspend an ongoing erase or program operation, and how is it controlled?
Yes, W25Q80BWZPIG supports Erase/Program Suspend via instruction 75h and Resume via 7Ah. This allows interrupt-driven systems to pause long-duration operations (e.g., 64 KB block erase) and resume them later without data corruption. The SUS bit in Status Register-1 indicates suspension state, and the feature is fully functional across all SPI modes - confirmed in Sections 7.1.8 and 7.2.27–7.2.28.
W25Q80BWZPIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 8Mbit
- Memory Organization:
- 1M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 80 MHz
- Write Cycle Time - Word, Page:
- 800µs
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25Q80BWZPIG FAQ
1.How can I place an order for W25Q80BWZPIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q80BWZPIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q80BWZPIG reliable?
The price and inventory of W25Q80BWZPIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q80BWZPIG is usually 5 days.
3.What payment methods are accepted for W25Q80BWZPIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q80BWZPIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q80BWZPIG?
W25Q80BWZPIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q80BWZPIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q80BWZPIG?
For technical support, including W25Q80BWZPIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q80BWZPIG requirements.
6.How does Aetrix verify that W25Q80BWZPIG is sourced from the original manufacturer or authorized distributors?
All W25Q80BWZPIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q80BWZPIG meets industry standards.
7.What is the process for return or replacement of W25Q80BWZPIG?
All W25Q80BWZPIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q80BWZPIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q80BWZPIG part is unused and in its original packaging.
Return procedure for W25Q80BWZPIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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