Winbond Electronics Corporation W25Q80DLSVIG
- Part No.:
- W25Q80DLSVIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
W25Q80DLSVIG.pdf
- Description:
- IC FLASH 8MBIT SPI/QUAD 8VSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,660
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q80DLSVIG from Winbond is an 8 M-bit (1 MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with hardware write protection, 4 KB uniform sectors, and 64-bit unique ID. It operates from 2.3 V to 3.6 V, supports up to 80 MHz dual/quad SPI clocks (160/320 MHz equivalent), and delivers 40 MB/s continuous read throughput. It is used for code execution (XIP), firmware storage, and parameter retention in microcontroller-based embedded systems.
For engineers reviewing the W25Q80DLSVIG datasheet, W25Q80DLSVIG pinout, W25Q80DLSVIG application, or W25Q80DLSVIG equivalent, key selection criteria include voltage range compatibility (2.3–3.6 V), Quad SPI enable requirement (QE bit), /WP and /HOLD pin reassignment in Quad mode, and sector/block erase granularity (4 KB/32 KB/64 KB).
Technical Context
The W25Q80DLSVIG implements a flexible SPI command architecture supporting three operational modes: Standard SPI (DI/DO), Dual SPI (IO0/IO1), and Quad SPI (IO0–IO3), where /WP and /HOLD become IO2 and IO3 only when the non-volatile Quad Enable (QE) bit in Status Register-2 is set. Its block diagram integrates a 256-byte page buffer, SFDP register for discoverable parameters, and three 256-byte security registers with OTP locks.
It features dual-level write protection: hardware via active-low /WP pin (disabled in Quad mode), and software via status register bits (BP2–BP0, TB, SEC, CMP, SRP0/SRP1). Erase/program suspend/resume capability enables interruptible operations, and JEDEC-compliant manufacturer/device ID plus 64-bit unique serial number support secure identification and traceability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 8 M-bit (1,048,576 bytes), organized as 4,096 × 256-byte pages |
| Supply Voltage | 2.3 V to 3.6 V - enables operation in low-voltage embedded systems including battery-powered designs |
| Max SPI Clock | 80 MHz for Dual/Quad mode - enables 160 MHz (Dual I/O) or 320 MHz (Quad I/O) effective throughput |
| Erase Granularity | Uniform 4 KB sectors, 32 KB blocks, 64 KB blocks - supports fine-grained firmware updates and data logging |
| Data Retention | 20+ years - ensures long-term reliability for industrial and automotive firmware storage |
| Endurance | 100,000 program/erase cycles - suitable for frequent field firmware updates and configuration logging |
| Unique ID | 64-bit factory-programmed serial number - enables device-level traceability and secure boot binding |
| Power-down Current | <1 µA (typ.) - minimizes standby power in always-on or energy-sensitive applications |
Pinout & Package
W25Q80DLSVIG is packaged in an 8-pin SOIC 208-mil (Package Code SS), with gull-wing leads and standard surface-mount footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable signal; must transition high→low after power-up before instruction acceptance |
| 2 DO (IO1) | Data Output / Bidirectional I/O1 | Unidirectional output in Standard SPI; bidirectional in Dual/Quad SPI for high-speed reads |
| 3 /WP (IO2) | Write Protect Input / Bidirectional I/O2 | Hardware write lock for status register; repurposed as IO2 when QE=1 (Quad mode) |
| 4 GND | Ground Reference | Primary return path for VCC and all I/O signals; requires low-impedance PCB connection |
| 5 DI (IO0) | Data Input / Bidirectional I/O0 | Unidirectional input in Standard SPI; bidirectional in Dual/Quad SPI for command/address/data |
| 6 CLK | Serial Clock Input | Synchronizes all SPI transfers; supports Mode 0 and Mode 3 clock polarity/idle states |
| 7 /HOLD (IO3) | Hold Input / Bidirectional I/O3 | Pauses ongoing SPI transaction; repurposed as IO3 when QE=1 (Quad mode) |
| 8 VCC | Power Supply | Single 2.3–3.6 V supply; requires local 0.1 µF ceramic decoupling adjacent to pin |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI Support | Enables 320 MHz effective read bandwidth via EBh/6Bh instructions - accelerates XIP and code shadowing |
| Erase/Program Suspend | Allows interruption of long erase/program cycles to service higher-priority tasks - improves real-time system responsiveness |
| Security Registers | Three 256-byte OTP-lockable registers - support secure key storage, calibration data, or license enforcement |
| SFDP Register | JEDEC-standard discoverable parameters - enables automatic driver configuration without hard-coded timing values |
| Top/Bottom Sector Protection | Configurable BP/TB bits allow locking boot code in top sectors while leaving application space writable - enhances firmware integrity |
| Low-Voltage Operation | 2.3 V minimum supply enables direct interfacing with 2.5 V or 3.3 V logic domains without level shifters |
Applications
| Industrial PLC Firmware Storage | Automotive Infotainment Boot Memory |
|---|---|
Use Scenario: Storing firmware images and configuration tables in programmable logic controllers operating in wide-temperature industrial environments. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Quad SPI interface for fast boot and runtime code fetch. Use Value: 4 KB sector granularity enables atomic firmware patching; 20-year data retention ensures reliability over equipment lifetime. |
Use Scenario: Hosting boot loader and OS kernel for head-unit microprocessors in automotive infotainment systems. IC Role / Device Role / Timing Role: Primary boot memory accessed via Quad SPI during cold start; supports secure boot via 64-bit unique ID. Use Value: 40 MB/s read throughput reduces boot time; OTP security registers store cryptographic keys resistant to replay attacks. |
| Medical Device Parameter Logging | Smart Meter Firmware & Calibration Data |
Use Scenario: Recording sensor calibration coefficients and usage logs in portable diagnostic equipment with strict power budgets. IC Role / Device Role / Timing Role: Low-power persistent storage with <1 µA deep-sleep current and hardware write protection against accidental overwrite. Use Value: /WP pin enables fail-safe write lockdown during critical measurements; 100,000-cycle endurance supports daily recalibration. |
Use Scenario: Storing firmware, tariff tables, and metrology calibration constants in ANSI C12.22-compliant smart electricity meters. IC Role / Device Role / Timing Role: Secure, field-upgradable memory with sector-level erase isolation to preserve billing history during OTA updates. Use Value: Top/bottom protection prevents bootloader corruption; SFDP register allows dynamic timing adaptation across meter generations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| W25Q80DVSSIG | Higher voltage range (2.7–3.6 V); 104 MHz Quad SPI clock; 50 MB/s read rate | Better suited for 3.3 V systems requiring maximum throughput; not compatible in 2.3–2.7 V designs | Select W25Q80DVSSIG only if system VCC ≥2.7 V and >40 MB/s read performance is required. |
| AT25SF041-SSHD-B | 4 M-bit density; 1.65–3.6 V operation; no Quad SPI; supports DTR mode | Lacks Quad I/O and 64-bit UID; lower density limits use to simpler firmware storage | Choose AT25SF041-SSHD-B only for cost-sensitive, low-density, non-XIP applications without Quad SPI dependency. |
Compared with W25Q80DLSVIG, W25Q80DVSSIG offers higher speed and voltage margin but sacrifices low-voltage operation, while AT25SF041-SSHD-B provides broader voltage range and DTR support at half the density and without Quad SPI or unique ID - making W25Q80DLSVIG the optimal balance of low-voltage capability, security, and performance for modern embedded boot and firmware storage.
Availability
W25Q80DLSVIG is available at Aetrix Electronics and suitable for industrial PLCs, automotive infotainment systems, medical diagnostics, smart meters, and IoT edge nodes requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for W25Q80DLSVIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial flash, RAM, and mobile DRAM, serving industrial, automotive, and consumer markets.
The W25Q series is designed for high-reliability embedded firmware and code storage, emphasizing Quad SPI performance, security features (UID, security registers), and robustness across extended temperature and voltage ranges.
FAQ
What voltage range does the W25Q80DLSVIG support?
The W25Q80DLSVIG operates from 2.3 V to 3.6 V, making it suitable for low-voltage embedded systems such as battery-powered sensors and 2.5 V logic domains. This differs from the W25Q80DV variant, which requires a minimum of 2.7 V. The 2.3 V lower limit enables direct integration without level-shifting circuitry in many portable designs, and the specification is validated across commercial and industrial temperature ranges.
Does the W25Q80DLSVIG support Quad SPI operation out of the box?
No - Quad SPI operation requires setting the non-volatile Quad Enable (QE) bit in Status Register-2 via the Write Status Register (01h) instruction. Until QE=1, pins /WP and /HOLD remain dedicated to hardware write protection and hold functions. After QE is set, those pins become IO2 and IO3, enabling full Quad I/O commands like EBh (Fast Read Quad I/O). This configuration persists across power cycles.
How is hardware write protection implemented on the W25Q80DLSVIG?
Hardware write protection on the W25Q80DLSVIG is enabled by pulling the /WP pin low, which locks writes to the status register (including BP bits and QE). This protection remains active regardless of the QE state - though /WP is reassigned to IO2 in Quad mode, its hardware protection function is disabled when QE=1. For full array protection, /WP must be used in conjunction with status register BP/TB bits to define protected sectors or blocks.
What is the purpose of the 64-bit Unique ID in the W25Q80DLSVIG?
Each W25Q80DLSVIG contains a factory-programmed, unalterable 64-bit Unique ID accessible via instruction 4Bh. This ID enables device-level traceability, secure boot binding (e.g., pairing with MCU public keys), and anti-cloning measures in certified applications. Unlike software-generated identifiers, it requires no user programming and is guaranteed unique across the entire Winbond production lot, supporting compliance with IEC 62443 and ISO/SAE 21434 requirements.
Can the W25Q80DLSVIG be used for Execute-in-Place (XIP) applications?
Yes - the W25Q80DLSVIG supports XIP via Fast Read Quad I/O (EBh) and Fast Read Quad Output (6Bh) instructions, delivering up to 320 MHz effective throughput. Its uniform 4 KB sector architecture allows precise mapping of executable code segments, and the 80 MHz Quad SPI clock meets timing requirements for most Cortex-M and RISC-V microcontrollers with SPI memory controllers. XIP performance is further enhanced by the 256-byte page buffer and suspend/resume capability for deterministic latency.
W25Q80DLSVIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 8Mbit
- Memory Organization:
- 1M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSOP
W25Q80DLSVIG FAQ
1.How can I place an order for W25Q80DLSVIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q80DLSVIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q80DLSVIG reliable?
The price and inventory of W25Q80DLSVIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q80DLSVIG is usually 5 days.
3.What payment methods are accepted for W25Q80DLSVIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q80DLSVIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q80DLSVIG?
W25Q80DLSVIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q80DLSVIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q80DLSVIG?
For technical support, including W25Q80DLSVIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q80DLSVIG requirements.
6.How does Aetrix verify that W25Q80DLSVIG is sourced from the original manufacturer or authorized distributors?
All W25Q80DLSVIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q80DLSVIG meets industry standards.
7.What is the process for return or replacement of W25Q80DLSVIG?
All W25Q80DLSVIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q80DLSVIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q80DLSVIG part is unused and in its original packaging.
Return procedure for W25Q80DLSVIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q80DLSVIG Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

