Winbond Electronics Corporation W25Q80DVSVIG
- Part No.:
- W25Q80DVSVIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
W25Q80DVSVIG.pdf
- Description:
- IC FLASH 8MBIT SPI/QUAD 8VSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q80DVSVIG from Winbond is an 8 M-bit (1 MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with uniform 4 KB sectors and up to 104 MHz clock frequency. It operates from a single 2.7–3.6 V supply, consumes <1 µA in power-down mode, and delivers 50 MB/s continuous read throughput via Quad I/O Fast Read (EBh). It is used for code shadowing, XIP execution, and firmware storage in microcontroller-based embedded systems.
For engineers reviewing the W25Q80DVSVIG datasheet, W25Q80DVSVIG pinout, W25Q80DVSVIG application, or W25Q80DVSVIG equivalent, key selection criteria include Quad SPI enable (QE bit), hardware write protection via /WP and /HOLD pins, 4 KB sector granularity for parameter storage, and SOIC-8 208-mil (SS) package compatibility with legacy PCB footprints.
Technical Context
The W25Q80DVSVIG implements a SPI-compatible command set with three operational modes: Standard SPI (DI/DO), Dual SPI (IO0/IO1), and Quad SPI (IO0–IO3), where /WP and /HOLD become IO2 and IO3 only when the non-volatile Quad Enable (QE) bit in Status Register-2 is set. Its architecture includes a 256-byte page buffer, 256 erasable 4 KB sectors, and 16 erasable 64 KB blocks.
It supports JEDEC-standard identification (9Fh), 64-bit unique ID (4Bh), SFDP register (5Ah), and security features including three 256-byte OTP-lockable security registers. Erase/program suspend/resume functionality enables concurrent background operations, and write protection combines volatile/non-volatile status bits with hardware /WP pin control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 8 M-bit (1,048,576 bytes), organized as 4,096 × 256-byte pages |
| Interface Support | Standard/Dual/Quad SPI; requires QE=1 for Quad I/O; IO2 (/WP) and IO3 (/HOLD) repurposed only when enabled |
| Max Clock Frequency | 104 MHz for Dual/Quad SPI; enables 208 MHz (Dual) or 416 MHz (Quad) effective throughput |
| Erase Granularity | Uniform 4 KB sectors, 32 KB blocks, 64 KB blocks, and full-chip erase - enables fine-grained firmware partitioning |
| Write Endurance | ≥100,000 program/erase cycles per sector - suitable for field-upgradable firmware with frequent minor updates |
| Data Retention | ≥20 years at +25°C - ensures long-term reliability in unattended industrial deployments |
| Supply Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic systems without level shifting |
| Power-Down Current | <1 µA (typ.) - critical for battery-backed or energy-harvesting applications requiring ultra-low standby drain |
Pinout & Package
W25Q80DVSVIG is packaged in 8-pin SOIC-208-mil (Package Code SS), with pin 1 marked by a notch or dot. All pins are surface-mount compatible and support reflow soldering per J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; must transition high→low after power-up before accepting instructions; controls DO high-impedance state |
| 2 DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad SPI; used for status/data reads on CLK falling edge |
| 3 /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware write lock for status register; becomes IO2 in Quad SPI only when QE=1; active-low |
| 4 GND | Ground Reference | Primary return path for VCC and all I/O signals; must be low-impedance and decoupled near device |
| 5 DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad SPI; accepts instructions/addresses on CLK rising edge |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference; supports SPI Modes 0 and 3; max 104 MHz; must be stable before /CS assertion |
| 7 /HOLD (IO3) | Hold Input / Bidirectional I/O | Pauses ongoing SPI transaction while /CS remains low; becomes IO3 in Quad SPI only when QE=1; active-low |
| 8 VCC | Power Supply | 2.7–3.6 V nominal; requires local 0.1 µF ceramic decoupling capacitor placed ≤3 mm from pin |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI with QE bit control | Enables 416 MHz effective read bandwidth (via EBh) and eliminates need for parallel bus routing in space-constrained designs |
| Uniform 4 KB sector erase | Allows independent firmware update of bootloader, application, and configuration partitions without disturbing adjacent data |
| Erase/Program Suspend & Resume | Permits interruption of long erase/program operations to service time-critical interrupts, then resume from exact point |
| 64-bit Unique Serial Number | Provides cryptographically traceable device identity for secure boot, anti-cloning, and field asset tracking |
| Three 256-byte Security Registers | Supports customer-defined keys, certificates, or calibration data with OTP locking to prevent overwrite in production |
| SFDP Register (5Ah) | Enables automatic, standardized detection of memory geometry, timing, and feature set by host bootloader or HAL layer |
Applications
| IoT Edge Node Firmware Storage | Industrial PLC Bootloader Memory |
|---|---|
|
Use Scenario: Storing signed firmware images and OTA update payloads in battery-powered wireless sensors with limited PCB area. IC Role / Device Role / Timing Role: Non-volatile code and configuration storage with Quad SPI XIP capability and hardware write protection during over-the-air updates. Use Value: 4 KB sector granularity enables atomic update of firmware segments; <1 µA power-down current extends multi-year battery life. |
Use Scenario: Holding certified bootloader and safety-critical application code in programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Trusted boot source with JEDEC ID verification, 20-year data retention, and hardware /WP pin lock during runtime. Use Value: OTP-locked security registers store cryptographic keys; uniform sector erase allows safe rollback to known-good firmware versions. |
| Medical Device Configuration Archive | Automotive Infotainment UI Assets |
|
Use Scenario: Archiving device-specific calibration parameters, usage logs, and regulatory audit trails in Class II medical instruments. IC Role / Device Role / Timing Role: Parameter storage with sector-level write protection and 100,000+ endurance cycles for frequent logging. Use Value: Independent 4 KB sectors isolate calibration data from logs; SFDP register simplifies HAL integration across product variants. |
Use Scenario: Caching graphical assets, voice prompts, and map tiles in automotive head units where fast random access reduces UI latency. IC Role / Device Role / Timing Role: High-bandwidth asset cache using Quad SPI Fast Read (EBh) to feed GPU or display controller directly. Use Value: 50 MB/s sustained read rate eliminates bottlenecks; 64 KB block erase enables efficient tile-set replacement during navigation updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L8006EM1I-12G | 8 M-bit, 3 V, SOIC-8 208-mil; max 86 MHz clock; no Quad I/O; lacks SFDP and unique ID | Lower-cost option for legacy SPI-only designs without XIP or secure boot requirements | Select when Quad SPI, SFDP, or device identity are not needed - avoids QE configuration complexity |
| S25FL008KAGMFI010 | 8 M-bit, 2.7–3.6 V; supports Quad SPI and SFDP; 133 MHz max clock; includes configurable reset pin | Better performance and enhanced reliability features (ECC, margin read), but larger footprint (16-pin SOIC) | Choose for mission-critical applications needing ECC or higher clock speed; verify PCB layout change for 16-pin package |
Compared with W25Q80DVSVIG, MX25L8006EM1I-12G offers simpler SPI operation but omits Quad I/O and identity features, while S25FL008KAGMFI010 adds ECC and speed at the cost of pin count and board space - W25Q80DVSVIG balances density, interface flexibility, and compact SOIC-8 packaging for mainstream embedded use.
Availability
W25Q80DVSVIG is available at Aetrix Electronics and suitable for IoT edge node firmware storage, industrial PLC bootloader memory, and medical device configuration archive applications requiring stable component supply, long-lifecycle support, and RoHS-compliant sourcing.
Supply support for W25Q80DVSVIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for embedded, communications, and consumer markets.
The W25Q series was designed to replace parallel NOR flash in resource-constrained systems, delivering SPI-based simplicity with Dual/Quad I/O performance, robust write protection, and industrial-grade reliability for code storage and data logging.
FAQ
What is the package type and lead count of W25Q80DVSVIG?
W25Q80DVSVIG uses an 8-pin SOIC-208-mil package (Package Code SS), with standard gull-wing leads and 1.27 mm pitch. It is RoHS-compliant, halogen-free, and qualified per JEDEC J-STD-020 for moisture sensitivity level 3. This package is pin-compatible with other W25Q80DV variants in SOIC-208-mil format and supports automated SMT assembly.
Does W25Q80DVSVIG support Quad SPI mode out of the box?
No - W25Q80DVSVIG requires the Quad Enable (QE) bit in Status Register-2 to be set to 1 before Quad SPI instructions (e.g., EBh) will function. By default, QE=0 after power-up or chip erase, so /WP and /HOLD remain dedicated hardware control pins until explicitly configured. The Write Status Register (01h) instruction must be used to set QE, and the change persists across power cycles.
How does hardware write protection work on W25Q80DVSVIG?
W25Q80DVSVIG implements hardware write protection via the /WP pin, which - when held low - prevents writes to the status register regardless of software commands. This complements software-based protection using BP0–BP2, TB, SEC, and CMP bits. /WP protection is active only in Standard and Dual SPI modes; it is disabled in Quad SPI because /WP becomes IO2 when QE=1.
What is the minimum erase unit size for W25Q80DVSVIG?
The minimum erase unit size for W25Q80DVSVIG is 4 KB, corresponding to one uniform sector. The device contains 256 such sectors. This granularity enables precise firmware updates - for example, erasing only the application partition while preserving bootloader and configuration sectors - and is essential for robust over-the-air update schemes in embedded systems.
Can W25Q80DVSVIG be used for Execute-in-Place (XIP) applications?
Yes - W25Q80DVSVIG supports XIP via Dual and Quad SPI Fast Read instructions (BBh and EBh), achieving up to 416 MHz effective throughput. When paired with a host MCU that supports memory-mapped SPI (e.g., certain ARM Cortex-M7/M33 or RISC-V SoCs), W25Q80DVSVIG allows direct code execution from flash without copying to RAM, reducing boot time and SRAM usage in resource-limited designs.
W25Q80DVSVIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 8Mbit
- Memory Organization:
- 1M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSOP
W25Q80DVSVIG FAQ
1.How can I place an order for W25Q80DVSVIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q80DVSVIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q80DVSVIG reliable?
The price and inventory of W25Q80DVSVIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q80DVSVIG is usually 5 days.
3.What payment methods are accepted for W25Q80DVSVIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q80DVSVIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q80DVSVIG?
W25Q80DVSVIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q80DVSVIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q80DVSVIG?
For technical support, including W25Q80DVSVIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q80DVSVIG requirements.
6.How does Aetrix verify that W25Q80DVSVIG is sourced from the original manufacturer or authorized distributors?
All W25Q80DVSVIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q80DVSVIG meets industry standards.
7.What is the process for return or replacement of W25Q80DVSVIG?
All W25Q80DVSVIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q80DVSVIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q80DVSVIG part is unused and in its original packaging.
Return procedure for W25Q80DVSVIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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