Winbond Electronics Corporation W25Q80EWZPIG
- Part No.:
- W25Q80EWZPIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q80EWZPIG.pdf
- Description:
- IC FLASH 8MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q80EWZPIG from Winbond is an 8 M-bit (1 MB) serial flash memory IC supporting Standard/Dual/Quad SPI and QPI interfaces, operating from 1.65V to 1.95V with 104 MHz max clock rate, 4 KB uniform sector erase granularity, and 1 µA power-down current. It serves as non-volatile code storage and XIP (execute-in-place) memory in microcontroller boot systems, IoT edge nodes, and firmware update modules.
For engineers reviewing the W25Q80EWZPIG datasheet, W25Q80EWZPIG pinout, W25Q80EWZPIG application, or W25Q80EWZPIG equivalent, key selection criteria include Quad Enable (QE) bit configuration, /WP and /HOLD pin reassignment in Quad mode, 4 KB sector protection granularity, and JEDEC-compliant SFDP register support for auto-configuration.
Technical Context
The W25Q80EWZPIG implements a flexible SPI command architecture with three operational modes: Standard SPI (DI/DO), Dual SPI (IO0/IO1), and Quad SPI/QPI (IO0–IO3). Its status register includes non-volatile Quad Enable (QE) bit in SR-2, which must be set to repurpose /WP and /HOLD as IO2 and IO3 - a hardware requirement for Quad I/O operation.
It features 256 uniform 4 KB sectors, 16 × 64 KB blocks, and supports Erase/Program Suspend & Resume. The device integrates 3 × 256-byte security registers with OTP locks, 64-bit unique serial number, and SFDP v1.5 register for parameter discovery - enabling runtime configuration without hard-coded timing values.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 8 M-bit (1,048,576 bytes), organized as 4,096 × 256-byte pages |
| Supply Voltage | 1.65 V to 1.95 V - enables direct interface with 1.8 V logic families without level shifters |
| Max Clock Frequency | 104 MHz SPI; 208 MHz equivalent Dual I/O; 416 MHz equivalent Quad I/O - supports >50 MB/s continuous read throughput |
| Erase Granularity | Uniform 4 KB sectors, 32 KB blocks, 64 KB blocks - allows fine-grained firmware partitioning and OTA update safety |
| Endurance & Retention | 100,000 program/erase cycles per sector; 20+ years data retention at +85°C - suitable for field-upgradable embedded systems |
| Interface Modes | Standard SPI (Mode 0/3), Dual SPI, Quad SPI, and QPI - selectable via instruction set; QPI reduces instruction overhead by 75% vs SPI |
| Security Features | Hardware /WP and /HOLD write protect, top/bottom/complement array lock, 64-bit UID, SFDP register, 3×256-byte OTP-lockable security registers |
Pinout & Package
W25Q80EWZPIG uses an 8-pin SOIC 208-mil package (package code SS), with pin 1 = /CS, pin 2 = DO (IO1), pin 3 = /WP (IO2), pin 4 = GND, pin 5 = DI (IO0), pin 6 = CLK, pin 7 = /HOLD (IO3), pin 8 = VCC. Pin functions change based on QE bit state: when QE=1, pins 3 and 7 become IO2 and IO3 for Quad I/O.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select input | Active-low enable; high-impedance DO during deselect; required low-to-high transition before new instruction acceptance |
| DO / IO1 (Pin 2) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional in Dual/Quad SPI/QPI; used for status/data reads on falling CLK edge |
| /WP / IO2 (Pin 3) | Write Protect input / Bidirectional I/O | Hardware write lock for status register when QE=0; becomes IO2 in Quad mode (QE=1); active-low |
| GND (Pin 4) | Ground reference | Primary return path for VCC and all I/O signals; requires low-inductance layout for high-speed timing compliance |
| DI / IO0 (Pin 5) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional in Dual/Quad SPI/QPI; accepts instructions/addresses on rising CLK edge |
| CLK (Pin 6) | Serial clock input | Synchronizes all SPI transfers; supports Mode 0 (CLK idle low) and Mode 3 (CLK idle high); timing critical up to 104 MHz |
| /HOLD / IO3 (Pin 7) | Hold input / Bidirectional I/O | Pauses ongoing transfer while /CS active when QE=0; becomes IO3 in Quad mode (QE=1); active-low |
| VCC (Pin 8) | Power supply | 1.65–1.95 V core supply; decoupling capacitor required within 1 cm for stable 104 MHz operation |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction latency by 75% vs SPI - only 2 clocks needed to send 8-bit opcodes using all four IOs |
| Erase/Program Suspend & Resume | Enables real-time interrupt handling during long erase/program cycles without data loss or timeout failure |
| JEDEC SFDP v1.5 Register | Allows host MCU to auto-detect timing parameters, voltage ranges, and feature sets - eliminating hardcoded flash initialization |
| 64-bit Unique Serial Number | Provides cryptographically secure device identity for firmware binding, anti-cloning, and secure boot key derivation |
| OTP-Lockable Security Registers | Three 256-byte regions with one-time-programmable locks - ideal for storing cryptographic keys, calibration data, or device-specific secrets |
Applications
| Boot Code Storage | Firmware Over-the-Air (OTA) |
|---|---|
Use Scenario: Storing primary bootloader and application firmware for ARM Cortex-M or RISC-V MCUs requiring fast, reliable cold-start execution. IC Role / Device Role / Timing Role: Non-volatile XIP memory providing deterministic 104 MHz Quad I/O read access to instruction stream during reset vector fetch. Use Value: Enables sub-100 ms boot time via 416 MHz equivalent Quad I/O bandwidth and eliminates external parallel NOR flash footprint. | Use Scenario: Hosting dual-bank firmware images in smart meters, industrial gateways, and medical sensors where field updates must preserve rollback capability. IC Role / Device Role / Timing Role: Secure, sector-protected storage for validated firmware binaries with atomic sector swap and CRC-verified write integrity. Use Value: 4 KB sector granularity allows independent update of bootloader, app, and config partitions without erasing full image - reducing update window and risk. |
| Secure Key Storage | IoT Edge Configuration |
Use Scenario: Holding device-unique cryptographic keys, TLS certificates, and attestation secrets in battery-powered edge nodes. IC Role / Device Role / Timing Role: Tamper-resistant OTP-locked security register bank with hardware write-disable after programming. Use Value: Prevents key extraction via bus snooping or flash dump; 3×256-byte regions allow separation of root CA, device cert, and session keys. | Use Scenario: Storing calibrated sensor offsets, network credentials, and regional regulatory settings in connected home devices. IC Role / Device Role / Timing Role: Parameter storage with hardware write-protection (/WP pin + BP bits) and software-controlled sector locking. Use Value: Ensures factory-set calibration survives firmware upgrades; top/bottom block protection prevents accidental overwrite of critical config sectors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q80DVSNIG | Same density and pinout; operates at 2.7–3.6 V; lacks QPI mode and SFDP register; no OTP security registers | Designed for legacy 3.3 V systems without need for QPI acceleration or auto-configuration | Select only if voltage compatibility and cost outweigh need for 1.8 V operation, QPI, or enhanced security |
| Micron MT25QL80ABB8E12-0SIT | 8 M-bit, 1.8 V, supports QPI and SFDP; rated for -40°C to +105°C; includes Deep Power-Down mode (<0.5 µA) | Targeted at extended temperature automotive and industrial control applications requiring higher thermal margin | Prefer when ambient exceeds +85°C or ultra-low standby current is mandatory; otherwise W25Q80EWZPIG offers identical feature set at lower cost |
Compared with W25Q80DVSNIG, W25Q80EWZPIG delivers QPI acceleration, SFDP auto-discovery, and OTP security - essential for modern secure boot and OTA architectures; versus MT25QL80ABB8E12-0SIT, it trades extended temperature rating for lower unit cost and proven qualification in consumer and industrial designs.
Availability
W25Q80EWZPIG is available at Aetrix Electronics and suitable for boot code storage, firmware OTA updates, secure key provisioning, and IoT edge configuration requiring stable component supply across production lifecycles.
Supply support for W25Q80EWZPIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.
The W25Q series targets embedded systems requiring high-speed, low-voltage, secure serial flash - optimized for XIP, OTA, and trusted execution environments in resource-constrained devices.
FAQ
What is the operating voltage range of the W25Q80EWZPIG?
The W25Q80EWZPIG operates from 1.65 V to 1.95 V. This narrow 1.8 V nominal range ensures compatibility with modern low-power microcontrollers and eliminates the need for level-shifting circuitry. Operation outside this range may cause undefined behavior or permanent damage. The device draws only 1 mA during active read operations and less than 1 µA in power-down mode, making it suitable for battery-powered applications.
Does the W25Q80EWZPIG support Quad SPI and QPI modes simultaneously?
No, the W25Q80EWZPIG supports Standard SPI, Dual SPI, Quad SPI, and QPI as mutually exclusive operational modes. QPI mode is entered only after issuing the "Enter QPI (38h)" instruction and requires the Quad Enable (QE) bit in Status Register-2 to be set. Once in QPI mode, all instructions must use the 4-wire QPI protocol; returning to SPI requires "Exit QPI (FFh)". The device powers up in Standard SPI mode by default.
How does the /WP and /HOLD pin behavior change when Quad Enable (QE) is set?
When QE = 0 (factory default), pin 3 functions as active-low /WP and pin 7 as active-low /HOLD. When QE = 1, both pins become bidirectional I/Os: pin 3 becomes IO2 and pin 7 becomes IO3, enabling full Quad SPI or QPI operation. The /WP and /HOLD functions are disabled in Quad mode. This reassignment is hardware-enforced and cannot be overridden by software.
What is the purpose of the SFDP register in the W25Q80EWZPIG?
The SFDP (Serial Flash Discoverable Parameters) register in the W25Q80EWZPIG is a JEDEC-standardized, read-only memory map that provides host MCUs with programmable timing parameters, voltage ranges, erase block sizes, and feature flags - eliminating hardcoded flash initialization. Accessed via instruction 5Ah, it enables portable, vendor-agnostic flash drivers and simplifies migration between flash variants without firmware changes.
Can the W25Q80EWZPIG be used for secure boot key storage?
Yes, the W25Q80EWZPIG includes three 256-byte security registers with one-time-programmable (OTP) lock bits. Once locked, these regions become read-only and resistant to overwrite - ideal for storing cryptographic keys, device certificates, or calibration secrets. Combined with hardware write protection via /WP pin and status register BP bits, it provides layered security for secure boot implementations in certified IoT and industrial devices.
W25Q80EWZPIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 8Mbit
- Memory Organization:
- 1M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 800µs
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25Q80EWZPIG FAQ
1.How can I place an order for W25Q80EWZPIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q80EWZPIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q80EWZPIG reliable?
The price and inventory of W25Q80EWZPIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q80EWZPIG is usually 5 days.
3.What payment methods are accepted for W25Q80EWZPIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q80EWZPIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q80EWZPIG?
W25Q80EWZPIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q80EWZPIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q80EWZPIG?
For technical support, including W25Q80EWZPIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q80EWZPIG requirements.
6.How does Aetrix verify that W25Q80EWZPIG is sourced from the original manufacturer or authorized distributors?
All W25Q80EWZPIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q80EWZPIG meets industry standards.
7.What is the process for return or replacement of W25Q80EWZPIG?
All W25Q80EWZPIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q80EWZPIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q80EWZPIG part is unused and in its original packaging.
Return procedure for W25Q80EWZPIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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