Winbond Electronics Corporation W25R128FVPIG
- Part No.:
- W25R128FVPIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25R128FVPIG.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:

- Shipping:

Inventory:4,072
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Product details
Overview
W25R128FVPIG from Winbond is a 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI interface and integrated Replay Protection Monotonic Counter (RPMC) security. It operates from 2.7V to 3.6V, supports up to 104MHz clock (416MHz equivalent Quad I/O), delivers 50MB/s continuous read, and features uniform 4KB sectors, 100,000 program/erase cycles, and 20-year data retention - deployed in secure boot firmware storage for industrial microcontrollers.
For engineers reviewing the W25R128FVPIG datasheet, W25R128FVPIG pinout, W25R128FVPIG application, or W25R128FVPIG equivalent, key selection criteria include Quad SPI XIP capability, RPMC cryptographic counter support, hardware /RESET availability, and SOIC-8 (208-mil) package compatibility with legacy PCB footprints.
Technical Context
The W25R128FVPIG implements a standard SPI Mode 0/3 interface with bidirectional IO0–IO3 pins enabling configurable instruction modes: Standard (DI/DO), Dual (IO0/IO1), or Quad (IO0–IO3). Its internal architecture includes a 256-byte page buffer, sector/block erase logic, and dedicated RPMC hardware engine executing HMAC-SHA-256 using four 32-bit monotonic counters.
RPMC operations require dedicated command sequences (e.g., 9Bh + subcode) to increment or read counters, with root key and HMAC key programmable into OTP-locked security registers. The device integrates volatile/non-volatile status register bits (BP0–BP2, TB, SEC, CMP, SRP0/SRP1, QE factory-set) and supports Erase/Program Suspend & Resume for real-time system responsiveness.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB) - sufficient for full MCU boot images plus configuration and firmware update partitions. |
| Interface Speed | 104 MHz SPI clock, 416 MHz Quad I/O equivalent - enables fast code shadowing and XIP execution without parallel bus overhead. |
| Erase Granularity | Uniform 4 KB sectors, 32 KB and 64 KB blocks - allows fine-grained firmware updates without erasing entire device. |
| Data Retention | 20 years at +85°C - ensures long-term reliability in industrial temperature environments. |
| Endurance | 100,000 program/erase cycles per sector - supports frequent field firmware updates over product lifetime. |
| Security Features | RPMC with HMAC-SHA-256, 3×256-byte OTP-locked security registers, 64-bit unique ID - provides hardware-rooted anti-replay protection for secure boot chains. |
| Operating Voltage | 2.7 V to 3.6 V - compatible with standard 3.3 V I/O domains and brown-out tolerant power supplies. |
| Temperature Range | −40°C to +85°C - qualified for extended industrial applications without derating. |
Pinout & Package
W25R128FVPIG uses the 8-pin SOIC 208-mil package (Package Code S), with exposed pad not present and no thermal pad requirement. Pin assignments are identical to VSOP 208-mil and PDIP 300-mil variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance outputs when deasserted; must transition high→low after power-up before first command. |
| 2 IO1 | Bidirectional Data I/O | Used for Standard/Dual SPI; functions as DO in Standard mode, IO1 in Dual/Quad; requires external pull-up if unused. |
| 3 IO2 | Bidirectional Data I/O | Active only in Quad SPI mode (e.g., Fast Read Quad I/O); unused in Standard/Dual configurations. |
| 4 GND | Ground Reference | Primary signal return; must be low-inductance connection to minimize SPI noise and timing skew. |
| 5 IO0 | Bidirectional Data I/O | Used for Standard/Dual SPI; functions as DI in Standard mode, IO0 in Dual/Quad; critical for command/address input. |
| 6 CLK | Serial Clock Input | Edge-triggered master clock; supports Mode 0 (CLK idle low) and Mode 3 (CLK idle high); timing-critical for setup/hold compliance. |
| 7 IO3 | Bidirectional Data I/O | Active only in Quad SPI mode; enables full 4-bit data bus for maximum throughput; unused in lower-speed modes. |
| 8 VCC | Power Supply | 2.7–3.6 V supply; requires local 100 nF ceramic decoupling placed ≤3 mm from pin to suppress switching noise. |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI XIP Support | Enables direct code execution from flash via EBh/E7h instructions - eliminates RAM copy latency and reduces BOM cost. |
| RPMC Hardware Engine | Dedicated HMAC-SHA-256 accelerator with four independent 32-bit monotonic counters - prevents replay attacks without CPU intervention. |
| Erase/Program Suspend | Allows pausing active erase/program operations to service high-priority reads - maintains real-time system responsiveness. |
| Volatile/Non-Volatile Write Protection | BP0–BP2, TB, SEC, CMP bits configurable in both volatile (power-loss reset) and non-volatile (OTP-lockable) modes - flexible field update control. |
| JEDEC SFDP Compliance | Standardized 64-byte Serial Flash Discoverable Parameters register - enables automatic driver configuration in Linux/U-Boot without hard-coded timing tables. |
| Unique 64-bit ID | Factory-programmed immutable serial number - used for device authentication, license binding, and secure provisioning workflows. |
Applications
| Secure Boot Storage | Firmware Over-the-Air (FOTA) |
|---|---|
Use Scenario: Storing signed bootloader and root-of-trust keys in tamper-resistant flash during manufacturing. IC Role / Device Role / Timing Role: Non-volatile storage with RPMC-enforced integrity verification on every boot sequence; executes XIP during early boot before DRAM initialization. Use Value: Prevents malicious firmware rollback or injection by cryptographically validating monotonic counter state against host controller expectations. | Use Scenario: Receiving encrypted firmware patches in connected industrial gateways with limited RAM. IC Role / Device Role / Timing Role: Dual/Quad SPI flash providing high-throughput, low-latency read/write for patch staging and atomic swap operations. Use Value: 50 MB/s continuous read and 4 KB sector granularity allow rapid patch validation and installation without disrupting real-time PLC control loops. |
| Industrial HMI Code Storage | Medical Device Configuration Archive |
Use Scenario: Hosting GUI assets, fonts, and localized strings for touch-based HMIs in factory automation panels. IC Role / Device Role / Timing Role: XIP-capable memory delivering burst reads to GPU or display controller via Quad SPI; supports fast screen transitions and animation rendering. Use Value: Eliminates 100+ ms RAM load delay per screen asset, reducing UI latency to <5 ms - critical for operator response time compliance. | Use Scenario: Archiving calibration logs, sensor history, and audit trails in Class II medical diagnostic equipment. IC Role / Device Role / Timing Role: High-reliability non-volatile storage with 20-year data retention and write-protection lock-down for regulatory traceability. Use Value: Ensures FDA 21 CFR Part 11 compliance via OTP-locked security registers and immutable 64-bit device ID for forensic log attribution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| W25Q128JVSNIQ | No RPMC; lacks HMAC-SHA-256 engine and monotonic counters; supports QPI mode but no factory-set QE bit. | Suitable for cost-sensitive, non-security-critical firmware storage where cryptographic replay protection is unnecessary. | Select W25Q128JVSNIQ only if security certification (e.g., IEC 62443) is not required and legacy QPI compatibility is prioritized. |
| AT25SF128A-SSHD-B | Includes Secure Area Lock (SAL) and 128-bit unique ID but no hardware RPMC; supports 80 MHz max clock (320 MHz Quad equiv.) vs. 104 MHz. | Valid for secure boot where SAL-based region locking suffices, but cannot replace W25R128FVPIG in HMAC-driven anti-replay protocols. | Choose AT25SF128A-SSHD-B when SAL-based partitioning meets security policy and lower throughput is acceptable. |
Compared with W25Q128JVSNIQ and AT25SF128A-SSHD-B, the W25R128FVPIG uniquely delivers hardware-accelerated RPMC with monotonic counters - making it the only option for systems requiring cryptographic proof of message freshness in flash-based boot and update workflows.
Availability
W25R128FVPIG is available at Aetrix Electronics and suitable for industrial HMI, secure boot firmware, and medical device configuration archiving requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.
Supply support for W25R128FVPIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash and PSRAM, serving industrial, automotive, and computing markets since 1987.
The W25R series was designed specifically for secure embedded systems requiring hardware-rooted anti-replay protection, combining high-speed Quad SPI performance with dedicated RPMC cryptographic engines for trusted boot and firmware update integrity.
FAQ
What is the package type and pin count of the W25R128FVPIG?
The W25R128FVPIG uses an 8-pin SOIC 208-mil package (Package Code S) with standard pinout: /CS, IO1, IO2, GND, IO0, CLK, IO3, VCC. It shares identical pin mapping with VSOP and PDIP variants, enabling drop-in replacement across form factors without layout changes.
Does the W25R128FVPIG support Quad SPI operation out of the box?
Yes, the W25R128FVPIG has Quad Enable (QE) bit factory-set and unchangeable, meaning Quad SPI mode is permanently enabled. IO0–IO3 are always active for Quad instructions like EBh (Fast Read Quad I/O), eliminating software configuration overhead during initialization.
How does the RPMC feature in the W25R128FVPIG prevent replay attacks?
The W25R128FVPIG implements RPMC using HMAC-SHA-256 with four 32-bit monotonic counters. Each read/write request must include a valid counter value signed with a secret key; the device rejects requests with stale or repeated counter values - blocking replay of intercepted commands or data.
What is the maximum continuous read speed achievable with the W25R128FVPIG?
The W25R128FVPIG achieves 50 MB/s continuous read throughput using Fast Read Quad I/O (EBh) at 104 MHz clock. This is measured under standard conditions (VCC = 3.0–3.6 V, TA = 25°C) and assumes optimal PCB layout with matched trace lengths and proper termination.
Can the W25R128FVPIG be used in place of older W25Q-series devices?
The W25R128FVPIG is pin-compatible with W25Q128FV in SOIC-8 packages and shares identical command sets for Standard/Dual/Quad SPI operations. However, its RPMC features, factory-set QE, and enhanced security registers require updated driver support - not a blind drop-in replacement without firmware validation.
W25R128FVPIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25R128FVPIG FAQ
1.How can I place an order for W25R128FVPIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25R128FVPIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25R128FVPIG reliable?
The price and inventory of W25R128FVPIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25R128FVPIG is usually 5 days.
3.What payment methods are accepted for W25R128FVPIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25R128FVPIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25R128FVPIG?
W25R128FVPIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25R128FVPIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25R128FVPIG?
For technical support, including W25R128FVPIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25R128FVPIG requirements.
6.How does Aetrix verify that W25R128FVPIG is sourced from the original manufacturer or authorized distributors?
All W25R128FVPIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25R128FVPIG meets industry standards.
7.What is the process for return or replacement of W25R128FVPIG?
All W25R128FVPIG units undergo pre-shipment inspection (PSI). If there is an issue with W25R128FVPIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25R128FVPIG part is unused and in its original packaging.
Return procedure for W25R128FVPIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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