Winbond Electronics Corporation W25R128FVSIQ
- Part No.:
- W25R128FVSIQ
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
W25R128FVSIQ.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25R128FVSIQ from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI interface and integrated Replay Protection Monotonic Counter (RPMC) security. It delivers 104MHz clock rate, 416MHz equivalent Quad I/O throughput, and supports XIP (execute-in-place) for embedded code storage in space-constrained IoT and industrial controllers.
For engineers reviewing the W25R128FVSIQ datasheet, W25R128FVSIQ pinout, W25R128FVSIQ application, or W25R128FVSIQ equivalent, key selection criteria include RPMC-enabled secure boot integrity, 4KB uniform sector architecture, JEDEC SFDP compliance, and support for hardware reset via /RESET pin on SOIC-16 packages - critical for automotive firmware updates and trusted execution environments.
Technical Context
The W25R128FVSIQ implements a Quad SPI interface with fixed QE bit (factory-set, unchangeable), enabling high-speed 4-line data transfers using instructions like Fast Read Quad I/O (EBh). Its RPMC subsystem uses HMAC-SHA-256 to authenticate read/write operations against four independent 32-bit monotonic counters, preventing replay attacks during firmware validation.
It features three 256-byte OTP-locked Security Registers, volatile/non-volatile status register bits (BP2–BP0, TB, SEC, CMP, SRP1/SRP0), and flexible write protection modes including top/bottom block lock, complement array protection, and individual sector locking via 36h/39h commands - all managed without external components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB) - sufficient for full MCU firmware images and secure boot assets in compact edge devices. |
| Supply Voltage | 2.7 V to 3.6 V - compatible with standard 3.3 V logic rails and tolerant of brown-out conditions down to 2.7 V. |
| Max Clock Frequency | 104 MHz - enables 416 MB/s peak Quad I/O bandwidth, outperforming parallel NOR in pin-count-constrained designs. |
| Erase/Program Cycles | 100,000 cycles - supports frequent over-the-air (OTA) firmware updates in field-deployed equipment. |
| Data Retention | 20 years - ensures long-term reliability for industrial control systems and medical devices with infrequent reprogramming. |
| Operating Temperature | −40°C to +85°C - qualified for extended temperature operation in automotive body electronics and outdoor gateways. |
| RPMC Counters | Four independent 32-bit monotonic counters - each addressable via 8-bit Counter_Address for granular secure boot partitioning. |
Pinout & Package
W25R128FVSIQ is supplied in an 8-pin SOIC 208-mil package (Package Code S), with pin 1 = /CS, pin 2 = IO1, pin 3 = IO2, pin 4 = GND, pin 5 = IO0, pin 6 = CLK, pin 7 = IO3, pin 8 = VCC. All I/O pins support bidirectional operation in Dual/Quad SPI modes; /CS must transition high-to-low after power-up to accept new instructions.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable: places device in high-impedance standby when high; required high-to-low transition post-power-up to initialize command acceptance. |
| IO0 (Pin 5) | Bidirectional Data I/O | Carries DI/DO in Standard/Dual SPI; serves as least-significant data line in Quad SPI; used for instruction/address/data transfer on rising/falling CLK edges. |
| IO1 (Pin 2) | Bidirectional Data I/O | Second data line in Dual/Quad SPI; enables 2x/4x throughput vs Standard SPI; shares function with DO in legacy mode. |
| IO2 (Pin 3) | Bidirectional Data I/O | Third data line in Quad SPI only; required for 4-line read/write; unused in Standard/Dual modes. |
| IO3 (Pin 7) | Bidirectional Data I/O | Fourth data line in Quad SPI only; completes full quad-lane interface; unused in Standard/Dual modes. |
| CLK (Pin 6) | Serial Clock Input | Edge-triggered timing reference: rising edge for input sampling, falling edge for output latching; supports SPI Mode 0 and Mode 3. |
| GND (Pin 4) | Ground Reference | Primary return path for all I/O and core logic; must be low-impedance and decoupled near VCC pin to suppress switching noise. |
| VCC (Pin 8) | Power Supply | Single 2.7–3.6 V supply for core and I/O; internal voltage regulators ensure stable operation across rail variation; 4 mA active current minimizes system power budget impact. |
Key Features
| Feature | Design Value |
|---|---|
| Replay Protection Monotonic Counter (RPMC) | Four independent 32-bit counters authenticated via HMAC-SHA-256 - prevents firmware rollback and cloning by enforcing strict monotonicity in secure boot sequences. |
| Quad SPI with Fixed QE Bit | Factory-programmed Quad Enable (QE) bit eliminates configuration risk during initialization - guarantees deterministic high-speed interface behavior without software setup errors. |
| Uniform 4 KB Sector Architecture | 2048 erasable sectors enable fine-grained firmware partitioning - allows atomic OTA updates to bootloader, kernel, and application segments without full-chip erase. |
| Three 256-Byte Security Registers | OTP-lockable registers store cryptographic keys, root certificates, or device-specific secrets - protected against readback and overwrite after programming. |
| JEDEC SFDP & Unique ID | Standardized Serial Flash Discoverable Parameters register and 64-bit unique serial number - enable automated toolchain identification and BOM traceability in mass production. |
| Erase/Program Suspend & Resume | Allows background erase or program to pause for higher-priority reads - essential for real-time systems requiring deterministic latency during flash maintenance. |
Applications
| Secure Boot Loader Storage | Firmware Over-the-Air (OTA) Update Storage |
|---|---|
Use Scenario: Storing immutable bootloader code and public key certificates in industrial PLCs where firmware authenticity must be verified before execution. IC Role / Device Role / Timing Role: Non-volatile storage element providing tamper-resistant code and cryptographic assets; RPMC counters enforce monotonic version progression during signature verification. Use Value: Prevents malicious rollback to vulnerable bootloader versions by binding counter state to signed firmware images - validated via HMAC-SHA-256 during each boot cycle. |
Use Scenario: Hosting dual firmware banks in smart metering endpoints that require seamless fail-safe updates without service interruption. IC Role / Device Role / Timing Role: Primary code storage with 4KB sector granularity enabling atomic swap between active/inactive firmware partitions; suspend/resume allows concurrent read access during background erase. Use Value: Enables zero-downtime field updates with guaranteed atomicity - sector-level locking ensures partial writes never corrupt operational firmware. |
| Embedded XIP Code Execution | Trusted Platform Module (TPM) Companion Storage |
Use Scenario: Executing real-time control algorithms directly from flash in automotive ADAS ECUs to reduce RAM footprint and boot latency. IC Role / Device Role / Timing Role: Memory-mapped Quad SPI device delivering 416 MB/s peak bandwidth; supports XIP with Fast Read Quad I/O (EBh) for deterministic instruction fetch timing. Use Value: Eliminates RAM copy overhead and reduces boot time by >30% compared to shadow-load architectures - critical for ASIL-B timing budgets. |
Use Scenario: Storing TPM attestation keys and platform configuration registers in server BMCs where hardware-rooted trust must persist across reboots. IC Role / Device Role / Timing Role: Secure non-volatile repository with OTP-locked Security Registers and individual sector locks - isolates sensitive keys from general-purpose firmware partitions. Use Value: Provides hardware-enforced separation between TPM keys and host firmware - prevents unauthorized extraction via JTAG or bus snooping due to physical write-protection and read-disable options. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash with security features applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Winbond W25Q128JVSIM | Lacks RPMC; uses standard Quad SPI with software-configurable QE; no HMAC-SHA-256 or monotonic counters. | Suitable for cost-sensitive consumer devices where secure boot is handled externally; not certified for automotive or industrial security requirements. | Select when RPMC is unnecessary and lower BOM cost is prioritized over hardware-enforced replay protection. |
| Cypress S25FL128SAGMFI00 | Includes 128-bit unique ID and SFDP but no dedicated RPMC engine; relies on external controller for monotonic counter management. | Used in networking infrastructure where flash acts as passive storage; security enforcement delegated to FPGA or SoC. | Choose when system-level security logic resides outside flash and deterministic counter hardware is not required. |
Compared with W25R128FVSIQ, W25Q128JVSIM offers identical density and speed but omits on-die cryptographic authentication, while S25FL128SAGMFI00 provides comparable reliability and SFDP support but shifts RPMC responsibility to the host - making W25R128FVSIQ the only option with integrated, hardware-enforced monotonicity for secure boot-critical applications.
Availability
W25R128FVSIQ is available at Aetrix Electronics and suitable for secure boot loader storage, firmware OTA update storage, embedded XIP code execution, and TPM companion storage requiring stable component supply across automotive, industrial, and IoT product lifecycles.
Supply support for W25R128FVSIQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for embedded and industrial markets.
The W25R series was designed specifically for systems demanding hardware-rooted security, featuring integrated RPMC and OTP-protected security registers to meet automotive functional safety and industrial cybersecurity standards.
FAQ
What is the primary security function enabled by the RPMC feature in W25R128FVSIQ?
The RPMC feature in W25R128FVSIQ provides hardware-enforced replay protection using four independent 32-bit monotonic counters authenticated via HMAC-SHA-256. Each counter increments only upward and cannot be reset or decremented, ensuring firmware images are executed in strict sequence - preventing attackers from rolling back to older, vulnerable versions during boot. This capability is intrinsic to W25R128FVSIQ and requires no external crypto engine.
Does W25R128FVSIQ support Quad SPI operation out of the box, or does it require configuration?
W25R128FVSIQ supports Quad SPI operation without software configuration because the Quad Enable (QE) bit is factory-set and unchangeable (per Section 7.1.10 of the datasheet). Unlike many competing flash devices, W25R128FVSIQ guarantees deterministic Quad I/O behavior from power-on - eliminating initialization risks and reducing firmware complexity in safety-critical systems.
Can W25R128FVSIQ be used for execute-in-place (XIP) applications, and what performance can be expected?
Yes, W25R128FVSIQ is optimized for XIP with Fast Read Quad I/O (EBh) instruction supporting up to 104 MHz clock frequency - delivering up to 416 MB/s effective throughput. Its uniform 4 KB sector architecture and erase/program suspend/resume functionality allow deterministic instruction fetch timing and background maintenance without interrupting real-time execution - validated in automotive ADAS and industrial PLC deployments.
How is write protection implemented in W25R128FVSIQ, and what levels of granularity are available?
W25R128FVSIQ implements multi-layer write protection including volatile/non-volatile status register bits (BP2–BP0, TB, SEC), complement array lock (CMP), and individual sector/block locking via 36h/39h commands. Protection granularity ranges from full chip (via SRP1/SRP0) to single 4 KB sectors - all enforced in hardware without CPU intervention. This architecture is confirmed in Sections 6.3 and 7.1 of the official datasheet.
What package type corresponds to the 'SIQ' suffix in W25R128FVSIQ, and what are its key mechanical properties?
The 'SIQ' suffix in W25R128FVSIQ denotes the 8-pin SOIC 208-mil package (Package Code S), measuring 5.3 mm × 5.3 mm × 1.95 mm with 1.27 mm lead pitch. This RoHS-compliant package features gull-wing leads, is rated for −40°C to +85°C operation, and is compatible with standard reflow profiles - confirmed in Section 10.1 and Figure 1a of the Winbond datasheet.
W25R128FVSIQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
W25R128FVSIQ FAQ
1.How can I place an order for W25R128FVSIQ through Aetrix?
Please submit a Request for Quotation (RFQ) for W25R128FVSIQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25R128FVSIQ reliable?
The price and inventory of W25R128FVSIQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25R128FVSIQ is usually 5 days.
3.What payment methods are accepted for W25R128FVSIQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25R128FVSIQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25R128FVSIQ?
W25R128FVSIQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25R128FVSIQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25R128FVSIQ?
For technical support, including W25R128FVSIQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25R128FVSIQ requirements.
6.How does Aetrix verify that W25R128FVSIQ is sourced from the original manufacturer or authorized distributors?
All W25R128FVSIQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25R128FVSIQ meets industry standards.
7.What is the process for return or replacement of W25R128FVSIQ?
All W25R128FVSIQ units undergo pre-shipment inspection (PSI). If there is an issue with W25R128FVSIQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25R128FVSIQ part is unused and in its original packaging.
Return procedure for W25R128FVSIQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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