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Winbond Electronics Corporation W25R128JVPIQ

Name: W25R128JVPIQ
Brand: Winbond Electronics Corporation
SKU: W25R128JVPIQ
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: W25R128JVPIQ

Manufacturer:: Winbond Electronics Corporation

Category:: Memory

Package:: 8-WDFN Exposed Pad

Datasheet:: W25R128JVPIQ.pdf

Description:: IC FLASH 128MBIT SPI/QUAD 8WSON

Quantity:: RFQ Add To RFQ list

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Product details

Overview

W25R128JVPIQ from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting standard, dual, and quad SPI interfaces with Replay Protection Monotonic Counter (RPMC) security. It operates from 2.7V to 3.6V, delivers up to 133MHz clock rate (532MHz equivalent in Quad I/O), features uniform 4KB sectors, and integrates three 256-byte security registers with OTP locks - deployed in secure boot firmware storage for industrial microcontrollers.

For engineers reviewing the W25R128JVPIQ datasheet, W25R128JVPIQ pinout, W25R128JVPIQ application, or W25R128JVPIQ equivalent, key selection criteria include RPMC support for hardware-verified firmware integrity, quad I/O throughput for XIP execution, individual block lock granularity, JEDEC SFDP compliance, and SOIC/WSON package compatibility with legacy PCB footprints.

Technical Context

The W25R128JVPIQ implements a SPI-compatible command set with mode-0/mode-3 clock polarity support, enabling interoperability with ARM Cortex-M, RISC-V, and FPGA-based controllers. Its architecture includes dedicated RPMC logic executing HMAC-SHA-256 authentication using four 32-bit monotonic counters addressed via 8-bit counter IDs.

Write protection is implemented through dual-layer control: non-volatile status register bits (BP2–BP0, TB, SEC, CMP, SRL) and volatile/OTP-configurable individual block locks per 64KB block or 4KB sector. The /RESET pin (available in SOIC-16 variant) provides hardware-level reset priority over all SPI operations.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	128 M-bit (16 MB) - supports full firmware images for mid-tier MCUs without external memory expansion.
Interface Speed	133 MHz SPI clock, 532 MHz equivalent Quad I/O - enables >60 MB/s sustained read for XIP execution.
Erase Granularity	Uniform 4 KB sectors, 32 KB and 64 KB blocks - allows fine-grained firmware update partitioning.
Data Retention	20 years at +85°C - validated for long-life industrial deployments without refresh cycles.
Endurance	100,000 program/erase cycles - sufficient for field-upgradable firmware with wear leveling.
Security Features	RPMC with HMAC-SHA-256, 64-bit unique ID, three 256-byte OTP-lockable security registers - meets IEC 62443-3-3 SL2 requirements for secure boot.
Operating Voltage	2.7 V to 3.6 V - compatible with 3.3 V system rails and tolerant of brown-out conditions.
Power Consumption	4 mA active current, <1 µA power-down (typ.) - suitable for battery-backed or low-power IoT edge nodes.

Pinout & Package

W25R128JVPIQ is packaged in an 8-pin SOIC 208-mil (Package Code S), with pin 1 marked by a notch or dot. This surface-mount package supports reflow soldering and fits standard 0.3-inch DIP footprints.

Pin/Terminal	Circuit Role	Design Meaning
/CS	Chip Select Input	Active-low enable; high-impedance outputs when deasserted; must track VCC during power-up/down.
IO0	Bidirectional Data I/O (DI/DO)	Used for Standard/Dual SPI input/output; primary data line for command/address/data transfer.
IO1	Bidirectional Data I/O	Enables Dual SPI reads/writes; becomes active in Fast Read Dual Output (3Bh) and Dual I/O (BBh) modes.
GND	Ground Reference	Signal and power return path; requires low-impedance connection to minimize noise coupling into SPI lines.
VCC	Power Supply	2.7–3.6 V supply; internal voltage regulator ensures stable core operation across rail variation.
IO2	Bidirectional Data I/O	Activated only in Quad SPI mode (e.g., Fast Read Quad I/O EBh); enables 4-bit parallel data transfer.
IO3	Bidirectional Data I/O	Completes Quad SPI interface; required for full 4-line bidirectional communication and RPMC command sequences.
CLK	Serial Clock Input	Edge-triggered timing reference; supports Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1).

Key Features

Feature	Design Value
RPMC Security	HMAC-SHA-256 authenticated monotonic counters prevent replay attacks on firmware updates and secure configuration storage.
Quad SPI XIP Support	Fast Read Quad I/O (EBh) enables direct code execution from flash at >60 MB/s, eliminating RAM shadowing latency.
Individual Block Lock	254 × 64KB blocks + 32 × 4KB top/bottom sectors each have independent lock bits - supports atomic firmware patching.
JEDEC SFDP Compliance	Standard Flash Discovery Parameter table allows automatic driver initialization and configuration without hard-coded parameters.
Low-Power Power-Down	<1 µA standby current with retention of lock state and register settings - ideal for always-on secure boot loaders.
Volatile/Non-Volatile Status Control	Status Register-1/2/3 bits (e.g., QE, WPS, DRV0/1) can be set as volatile (reset on power cycle) or non-volatile (OTP or latch-controlled).

Applications

Secure Boot Storage	Firmware Over-the-Air (FOTA)
Use Scenario: Storing signed bootloader and root-of-trust keys in tamper-resistant flash for automotive ECUs. IC Role / Device Role / Timing Role: Primary non-volatile storage for immutable boot code and cryptographic keys; accessed during cold start before DRAM initialization. Use Value: RPMC prevents rollback attacks by enforcing monotonic counter validation during signature verification, ensuring only newer firmware versions execute.	Use Scenario: Field-updating firmware on industrial gateways with zero-downtime patching capability. IC Role / Device Role / Timing Role: Dual-bank storage medium holding active and candidate firmware images; managed via sector erase and page program commands. Use Value: Uniform 4KB sector erase enables atomic image swap with <50 ms latency; individual block locks protect active bank during update.
Real-Time OS Kernel Storage	Secure Configuration Vault
Use Scenario: Hosting RTOS kernel and critical drivers in flash for deterministic boot on robotics controllers. IC Role / Device Role / Timing Role: XIP-capable memory mapped directly to CPU address space via QSPI peripheral; accessed via memory-mapped reads. Use Value: 133 MHz Quad SPI clock yields ~66 MB/s random read bandwidth - sufficient for real-time interrupt latency under 10 µs.	Use Scenario: Storing encrypted device credentials, calibration data, and TLS certificates in isolated flash regions. IC Role / Device Role / Timing Role: Secure register-backed storage using three 256-byte OTP-lockable security registers and individual sector locks. Use Value: OTP-enabled security register locks prevent runtime modification of cryptographic material, meeting FIPS 140-2 Level 2 physical security requirements.

Secure Boot Storage

Firmware Over-the-Air (FOTA)

Use Scenario: Storing signed bootloader and root-of-trust keys in tamper-resistant flash for automotive ECUs.

IC Role / Device Role / Timing Role: Primary non-volatile storage for immutable boot code and cryptographic keys; accessed during cold start before DRAM initialization.

Use Value: RPMC prevents rollback attacks by enforcing monotonic counter validation during signature verification, ensuring only newer firmware versions execute.

Use Scenario: Field-updating firmware on industrial gateways with zero-downtime patching capability.

IC Role / Device Role / Timing Role: Dual-bank storage medium holding active and candidate firmware images; managed via sector erase and page program commands.

Use Value: Uniform 4KB sector erase enables atomic image swap with <50 ms latency; individual block locks protect active bank during update.

Real-Time OS Kernel Storage

Secure Configuration Vault

Use Scenario: Hosting RTOS kernel and critical drivers in flash for deterministic boot on robotics controllers.

IC Role / Device Role / Timing Role: XIP-capable memory mapped directly to CPU address space via QSPI peripheral; accessed via memory-mapped reads.

Use Value: 133 MHz Quad SPI clock yields ~66 MB/s random read bandwidth - sufficient for real-time interrupt latency under 10 µs.

Use Scenario: Storing encrypted device credentials, calibration data, and TLS certificates in isolated flash regions.

IC Role / Device Role / Timing Role: Secure register-backed storage using three 256-byte OTP-lockable security registers and individual sector locks.

Use Value: OTP-enabled security register locks prevent runtime modification of cryptographic material, meeting FIPS 140-2 Level 2 physical security requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MX25L12833FZNI-08G	No RPMC; supports only standard/dual/quad SPI; lacks monotonic counters and HMAC engine.	Suitable for cost-sensitive designs where firmware authenticity is enforced externally (e.g., via MCU crypto engine).	Select when security is handled at SoC level and lower BOM cost is prioritized over integrated flash-side protection.
S25FL128SAGMFI000	Includes HyperBus interface and 166 MHz DDR mode; no RPMC but offers SFDP v1.6 and configurable dummy cycles.	Better suited for high-bandwidth display or video buffer applications requiring >100 MB/s burst reads.	Choose when system demands higher throughput than Quad SPI provides and HyperBus controller is available.

Compared with MX25L12833FZNI-08G and S25FL128SAGMFI000, the W25R128JVPIQ uniquely integrates hardware-enforced replay protection at the flash layer - eliminating dependency on host processor resources for monotonic counter management and HMAC computation.

Availability

W25R128JVPIQ is available at Aetrix Electronics and suitable for secure boot storage, firmware over-the-air updates, and real-time OS kernel hosting requiring stable component supply across automotive, industrial automation, and medical device production cycles.

Supply support for W25R128JVPIQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial flash, mobile DRAM, and code storage devices for embedded systems.

The W25R series was designed specifically for secure, high-reliability firmware storage in resource-constrained environments - integrating RPMC, OTP-protected security registers, and robust write protection to meet automotive ASIL-B and industrial functional safety requirements.

FAQ

What is the package type and footprint compatibility of W25R128JVPIQ?

W25R128JVPIQ uses an 8-pin SOIC 208-mil package (Package Code S) with standard 0.3-inch width and 0.050-inch pin pitch. It shares footprint compatibility with legacy Winbond W25Q and W25X series SOIC parts, enabling drop-in replacement in existing designs without PCB revision - provided /RESET functionality is not required, as W25R128JVPIQ does not include a dedicated /RESET pin in this variant.

Does W25R128JVPIQ support Quad SPI mode out of the box?

W25R128JVPIQ supports Quad SPI mode but requires enabling the Quad Enable (QE) bit in Status Register-1 via Write Status Register-1 (01h) instruction. By default, QE is cleared (0), so standard SPI operation is active after power-up. Once QE is set, IO2 and IO3 become active for bidirectional quad data transfer, and Fast Read Quad I/O (EBh) becomes functional.

How does the Replay Protection Monotonic Counter (RPMC) function in W25R128JVPIQ?

W25R128JVPIQ implements RPMC using four independent 32-bit monotonic counters, each addressable via an 8-bit counter ID. Each counter increments only upon successful HMAC-SHA-256-verified read/write access. The counters cannot be decremented or reset externally, preventing replay of stale firmware or configuration data - a core requirement for secure boot chains in automotive and industrial systems.

What write protection mechanisms are available on W25R128JVPIQ?

W25R128JVPIQ offers layered write protection: (1) status register-based (BP2–BP0, TB, SEC, CMP), (2) individual block/sector locks (254 blocks + 32 sectors), and (3) OTP-locked security registers. The WPS bit selects between register-based and individual lock schemes. All protections persist through power cycles unless explicitly unlocked via 39h (Individual Unlock) or 98h (Global Unlock) commands.

Is W25R128JVPIQ compatible with JEDEC-standard SFDP?

Yes, W25R128JVPIQ fully complies with JEDEC JESD216B SFDP v1.5. It exposes a standardized parameter table via Read SFDP Register (5Ah) instruction, enabling automatic driver detection of density, erase granularity, timing parameters, and supported instruction sets - reducing BSP development time and improving portability across MCU platforms.

W25R128JVPIQ Specifications

Product attributes: Attribute value

Manufacturer:: Winbond Electronics Corporation

Series:: SpiFlash®

Package/Case:: 8-WDFN Exposed Pad

Packaging:: Tube

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: FLASH

Technology:: FLASH - NOR

Memory Size:: 128Mbit

Memory Organization:: 16M x 8

Memory Interface:: SPI - Quad I/O

Clock Frequency:: 104 MHz

Write Cycle Time - Word, Page:: 3ms

Access Time:: -

Voltage - Supply:: 2.7V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-WSON (6x5)

W25R128JVPIQ FAQ

1.How can I place an order for W25R128JVPIQ through Aetrix?

Please submit a Request for Quotation (RFQ) for W25R128JVPIQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for W25R128JVPIQ reliable?

The price and inventory of W25R128JVPIQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25R128JVPIQ is usually 5 days.

3.What payment methods are accepted for W25R128JVPIQ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25R128JVPIQ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for W25R128JVPIQ?

W25R128JVPIQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your W25R128JVPIQ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for W25R128JVPIQ?

For technical support, including W25R128JVPIQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25R128JVPIQ requirements.

6.How does Aetrix verify that W25R128JVPIQ is sourced from the original manufacturer or authorized distributors?

All W25R128JVPIQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25R128JVPIQ meets industry standards.

7.What is the process for return or replacement of W25R128JVPIQ?

All W25R128JVPIQ units undergo pre-shipment inspection (PSI). If there is an issue with W25R128JVPIQ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The W25R128JVPIQ part is unused and in its original packaging.

Return procedure for W25R128JVPIQ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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