Winbond Electronics Corporation W25X10CLUXIG TR
- Part No.:
- W25X10CLUXIG TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
W25X10CLUXIG TR.pdf
- Description:
- IC FLASH 1MBIT SPI 104MHZ 8USON
- Quantity:
- Payment:

- Shipping:

Inventory:101
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Product details
Overview
W25X10CLUXIG TR from Winbond is a 1 M-bit (128 KB) serial flash memory IC supporting standard SPI, dual-output SPI, and dual I/O SPI interfaces with 4 KB uniform sectors, 104 MHz max clock frequency, and true execute-in-place (XIP) capability via Continuous Read Mode - used for code storage and parameter retention in space-constrained embedded microcontrollers and IoT edge nodes.
For engineers reviewing the W25X10CLUXIG TR datasheet, W25X10CLUXIG TR pinout, W25X10CLUXIG TR application, or W25X10CLUXIG TR equivalent, key selection considerations include its 2.3–3.6 V single-supply operation, hardware /WP and /HOLD control, JEDEC-compliant identification, 4 KB sector granularity for fine-grained data updates, and USON 2×3-mm package compatibility with high-density PCB layouts.
Technical Context
The W25X10CLUXIG TR implements a SPI-compatible serial interface with support for Modes 0 and 3, enabling interoperability with ARM Cortex-M, RISC-V, and legacy MCU host controllers. Its dual I/O mode uses bidirectional IO0/IO1 pins to achieve 208 Mbps effective throughput via BBh instruction, matching parallel flash performance while reducing pin count.
Internally, the device features a 512-page (256-byte/page) array organized into 32 × 4 KB sectors, 4 × 32 KB blocks, and 2 × 64 KB blocks. Write protection is enforced through volatile WEL latch, non-volatile BP/TB/SRP bits in an 8-bit status register, and hardware /WP pin logic - allowing selective top/bottom array locking without firmware intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 1 M-bit (131,072 bytes), organized as 512 × 256-byte pages - enables compact firmware image storage with minimal page buffer overhead. |
| Supply Voltage | 2.3 V to 3.6 V - compatible with 3.3 V and mixed-voltage systems; eliminates need for level shifters in most MCU designs. |
| Max Clock Frequency | 104 MHz (standard SPI); 208 MHz equivalent with Fast Read Dual I/O (BBh) - supports real-time code shadowing and XIP execution. |
| Erase Granularity | Uniform 4 KB sectors, plus 32 KB and 64 KB blocks - allows flexible field-upgrade partitioning (e.g., bootloader + app + config). |
| Endurance & Retention | 100,000 program/erase cycles; >20 years data retention - suitable for industrial logging and infrequently updated configuration storage. |
| Operating Temperature | –40 °C to +85 °C - qualified for automotive cabin modules, industrial HMIs, and outdoor sensor nodes. |
| Power Consumption | 1 mA active current; <1 µA power-down current - extends battery life in always-on low-power IoT endpoints. |
Pinout & Package
W25X10CLUXIG TR is packaged in an 8-pad USON (2 mm × 3 mm, 0.45 mm pitch) with wettable flank leads - optimized for automated optical inspection (AOI) and high-yield reflow in compact consumer and medical PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; must transition high→low after power-up before first instruction; high-impedance DO during deselect. |
| 2 DO / IO1 | Bidirectional Data Output / I/O | Standard SPI output (DO) or dual I/O lane (IO1); supports Fast Read Dual Output (3Bh) and Dual I/O (BBh) modes. |
| 3 /WP | Write Protect Input | Hardware lock for status register; active-low; works with SRP bit to enforce non-volatile write protection. |
| 4 GND | Ground Reference | Primary return path for VCC and I/O; requires low-inductance connection to minimize noise during fast read/write transitions. |
| 5 DI / IO0 | Bidirectional Data Input / I/O | Standard SPI input (DI) or dual I/O lane (IO0); carries instructions, addresses, and data on rising CLK edge. |
| 6 CLK | Serial Clock Input | Master-generated timing signal; supports Modes 0 and 3; determines maximum interface speed and setup/hold margins. |
| 7 /HOLD | Hold Input | Pauses ongoing SPI transaction without deselecting device; enables multi-peripheral bus sharing with deterministic resume. |
| 8 VCC | Power Supply | 2.3–3.6 V supply; internal voltage regulator ensures stable core operation across full range; decoupling capacitor required. |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | As few as 16 clocks to initiate address access - reduces instruction overhead and enables true XIP execution from flash without RAM copy. |
| Dual I/O SPI Interface | BBh instruction delivers 208 Mbps effective bandwidth using only two I/O pins - replaces 8-bit parallel interfaces while saving 6+ MCU pins. |
| Flexible Hardware Write Protection | /WP pin + TB/BP bits allow top/bottom 64 KB or arbitrary 4 KB sector locking - prevents accidental firmware corruption during field updates. |
| JEDEC ID & Unique Serial Number | 9Fh command returns manufacturer/device ID; 4Bh reads 64-bit unique ID - enables secure device authentication and BOM traceability. |
| Low-Power Power-Down Mode | B9h instruction reduces current to <1 µA; ABh wakes device and returns Device ID - ideal for battery-powered sleep/wake cycles. |
Applications
| Firmware Code Storage | Industrial Sensor Configuration |
|---|---|
Use Scenario: Storing boot firmware and application binaries for ARM Cortex-M4 microcontrollers in factory automation PLCs. IC Role / Device Role / Timing Role: Non-volatile code memory accessed via SPI XIP mode during cold start and runtime patch loading. Use Value: 4 KB sector erase enables incremental firmware updates without full chip erase; 104 MHz clock supports sub-100 ms boot time. |
Use Scenario: Retaining calibrated sensor offsets, compensation tables, and device-specific thresholds in wireless temperature/humidity nodes. IC Role / Device Role / Timing Role: Parameter storage with frequent small writes and infrequent full-sector rewrites. Use Value: 100,000-cycle endurance and 20-year retention ensure reliable operation over product lifetime without recalibration. |
| Consumer Electronics UI Assets | Medical Device Bootloader Storage |
Use Scenario: Holding GUI assets (fonts, icons, splash screens) in smart home hubs where PCB area is constrained. IC Role / Device Role / Timing Role: High-density serial memory interfaced to low-pin-count application processors via dual I/O SPI. Use Value: USON 2×3-mm footprint saves >60% board area vs. SOIC; 208 Mbps dual I/O bandwidth renders assets with no perceptible latency. |
Use Scenario: Securing certified bootloader images in Class IIa medical infusion pumps requiring tamper-resistant firmware integrity. IC Role / Device Role / Timing Role: Trusted boot memory with hardware write protection and JEDEC ID verification at power-on. Use Value: /WP pin + SRP/BP bits prevent unauthorized modification; 64-bit unique ID enables per-unit cryptographic binding. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF011-SSH-T | 1 M-bit, 2.7–3.6 V supply, 85 MHz max SPI clock, SOIC-8 only - lacks dual I/O mode and Continuous Read Mode. | Lower bandwidth limits XIP feasibility; no USON option restricts layout flexibility in ultra-compact designs. | Choose when cost sensitivity outweighs speed and package size requirements; verify /HOLD and /WP timing compatibility. |
| S25FL004KAGNFI011 | 4 M-bit density, 2.7–3.6 V, 104 MHz, supports Quad SPI (QPI) - larger capacity but higher VMIN and no 2.3 V support. | Over-provisioned memory may increase BOM cost; QPI requires additional MCU GPIOs not needed by W25X10CLUXIG TR's dual I/O. | Prefer when future firmware growth is certain and Quad SPI infrastructure already exists; avoid if 2.3 V operation or USON is mandatory. |
Compared with AT25DF011-SSH-T and S25FL004KAGNFI011, the W25X10CLUXIG TR uniquely balances 2.3 V operation, USON 2×3-mm packaging, dual I/O bandwidth, and 4 KB sector granularity - making it optimal for next-generation battery-powered and space-limited embedded systems where power, size, and interface efficiency are co-constrained.
Availability
W25X10CLUXIG TR is available at Aetrix Electronics and suitable for industrial IoT gateways, portable medical diagnostics, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.
Supply support for W25X10CLUXIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial flash, PSRAM, and code storage devices for embedded and communications markets.
The W25X series was designed specifically for code download, XIP execution, and parameter storage in resource-constrained microcontroller systems - emphasizing low voltage operation, small footprint packaging, and SPI protocol flexibility.
FAQ
What is the package type and lead count of the W25X10CLUXIG TR?
The W25X10CLUXIG TR uses an 8-pad USON (Ultra Thin Small Outline No-lead) package measuring 2 mm × 3 mm with 0.45 mm pitch. It has no external leads; solderable wettable flanks enable reliable AOI and reflow inspection. This differs from the SOIC-8 variant (W25X10CLSNIG TR) and confirms the UX package code in the part number.
Does the W25X10CLUXIG TR support Quad SPI (QSPI) mode?
No, the W25X10CLUXIG TR does not support Quad SPI. It supports standard SPI (single I/O), dual-output SPI (3Bh), and dual I/O SPI (BBh) only. Quad SPI functionality requires separate IO2/IO3 pins and command set extensions not implemented in the W25X10CLUXIG TR silicon - confirmed by its pinout (8 pins total) and instruction set documentation.
What is the minimum supply voltage required for reliable operation of the W25X10CLUXIG TR?
The W25X10CLUXIG TR operates reliably from 2.3 V to 3.6 V. Below 2.3 V, the device enters reset state and ignores all instructions - verified by absolute maximum ratings and power-up timing specifications (VWI threshold). This 2.3 V lower limit enables direct interfacing with 2.5 V or 2.8 V system rails without regulators.
How many program/erase cycles does the W25X10CLUXIG TR guarantee?
The W25X10CLUXIG TR guarantees a minimum of 100,000 program/erase cycles per sector, as specified in the "Features" section and electrical characteristics table. This endurance rating applies uniformly across all 4 KB sectors and is validated under standard operating conditions (–40 °C to +85 °C, VCC = 2.3–3.6 V).
Can the W25X10CLUXIG TR be used for Execute-in-Place (XIP) applications?
Yes, the W25X10CLUXIG TR supports true XIP via its Continuous Read Mode, which reduces instruction overhead to as few as 16 clocks for address setup. When combined with Fast Read Dual I/O (BBh), this enables deterministic, low-latency code execution directly from flash - confirmed by functional description and timing diagrams in the datasheet revision G.
W25X10CLUXIG TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 800µs
- Access Time:
- -
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-USON (2x3)
W25X10CLUXIG TR FAQ
1.How can I place an order for W25X10CLUXIG TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25X10CLUXIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25X10CLUXIG TR reliable?
The price and inventory of W25X10CLUXIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25X10CLUXIG TR is usually 5 days.
3.What payment methods are accepted for W25X10CLUXIG TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25X10CLUXIG TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25X10CLUXIG TR?
W25X10CLUXIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25X10CLUXIG TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25X10CLUXIG TR?
For technical support, including W25X10CLUXIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25X10CLUXIG TR requirements.
6.How does Aetrix verify that W25X10CLUXIG TR is sourced from the original manufacturer or authorized distributors?
All W25X10CLUXIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25X10CLUXIG TR meets industry standards.
7.What is the process for return or replacement of W25X10CLUXIG TR?
All W25X10CLUXIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25X10CLUXIG TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25X10CLUXIG TR part is unused and in its original packaging.
Return procedure for W25X10CLUXIG TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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