Winbond Electronics Corporation W25X10CLZPIG TR
- Part No.:
- W25X10CLZPIG TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25X10CLZPIG TR.pdf
- Description:
- IC FLASH 1MBIT SPI 104MHZ 8WSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25X10CLZPIG TR from Winbond is a 1 M-bit (128 KB) serial flash memory IC supporting standard SPI, dual-output SPI, and dual I/O SPI interfaces with 4 KB uniform sectors, 104 MHz max clock, and 208 Mbps effective data rate. It operates from 2.3 V to 3.6 V, draws 1 mA active and <1 µA in power-down, and targets embedded boot code storage and parameter retention in space-constrained industrial controllers.
For engineers reviewing the W25X10CLZPIG TR datasheet, W25X10CLZPIG TR pinout, W25X10CLZPIG TR application, or W25X10CLZPIG TR equivalent, this page delivers verified electrical specs, SOIC-8 and USON-2x3-mm package mapping, hardware/software write protection details, XIP-capable continuous read mode timing, and two validated alternative serial flash parts for migration or sourcing flexibility.
Technical Context
The W25X10CLZPIG TR implements a SPI-compatible serial interface with support for Modes 0 and 3, enabling interoperability with standard microcontroller SPI peripherals. Its dual I/O SPI mode uses bidirectional IO0/IO1 pins to achieve 208 Mbps throughput via BBh instruction, matching parallel flash performance while reducing pin count.
Internally, the device features a 512-page (256-byte/page) array organized into 32 × 4 KB sectors, 4 × 32 KB blocks, and 2 × 64 KB blocks - all erasable independently. The status register includes non-volatile BP0/BP1/TB bits and SRP bit, enabling granular top/bottom hardware-locked memory protection when combined with the /WP pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 1 M-bit (131,072 bytes), organized as 512 × 256-byte pages - enables compact firmware image storage with fine-grained update capability. |
| Supply Voltage | 2.3 V to 3.6 V - compatible with 2.5 V, 3.0 V, and 3.3 V logic domains without level shifting. |
| Max SPI Clock | 104 MHz - supports high-speed boot loading; dual I/O mode yields 208 Mbps effective bandwidth for XIP execution. |
| Erase Granularity | Uniform 4 KB sectors, plus 32 KB and 64 KB blocks - allows selective firmware patching without full chip erase. |
| Endurance & Retention | 100,000 program/erase cycles; >20 years data retention - suitable for field-upgradable embedded systems with infrequent writes. |
| Operating Temp | –40 °C to +85 °C - qualified for industrial temperature range operation without derating. |
| Power Consumption | 1 mA active current; <1 µA power-down current - extends battery life in always-on IoT sensor nodes. |
Pinout & Package
W25X10CLZPIG TR is available in two RoHS-compliant packages: 8-pin SOIC-150-mil (SN) and 8-pad USON-2×3-mm (UX). Both share identical pin functions and logic-level compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable: drives DO/IO pins to high-Z when high; required low-to-high transition at power-up before instruction acceptance. |
| DO (IO1) | Serial Data Output / Dual I/O | Unidirectional output in standard SPI; bidirectional I/O in dual modes - carries MSB-first data on falling CLK edge. |
| /WP | Write Protect Input | Hardware lock for status register: when low and SRP=1, prevents BP/TB/SRP changes - enables immutable factory configuration. |
| GND | Ground Reference | Primary return path for VCC and I/O signals; must be low-impedance to maintain timing integrity during fast SPI transfers. |
| DI (IO0) | Serial Data Input / Dual I/O | Unidirectional input in standard SPI; bidirectional I/O in dual modes - accepts instructions/addresses on rising CLK edge. |
| CLK | Serial Clock Input | Synchronous timing reference: supports Modes 0 and 3; requires stable edge alignment with /CS for reliable command latching. |
| /HOLD | Hold Input | Pauses ongoing SPI transaction: asserts high-Z on DO and ignores DI/CLK while /CS remains low - enables multi-device bus sharing. |
| VCC | Power Supply | Single 2.3–3.6 V supply: powers core logic and I/O buffers; internal voltage regulator ensures consistent timing across voltage range. |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | Enables true XIP: only 16 clocks overhead to initiate address fetch - eliminates instruction latency bottlenecks in MCU boot sequences. |
| Dual I/O SPI Interface | BBh instruction doubles throughput vs standard SPI - reduces firmware load time by >50% in resource-constrained MCUs. |
| Hardware Write Protection | /WP pin + SRP bit combination prevents accidental status register modification - critical for certified bootloader integrity. |
| Uniform 4 KB Sector Architecture | Allows independent erase of parameter regions without disturbing adjacent firmware - simplifies over-the-air update partitioning. |
| 64-bit Unique ID | Factory-programmed serial number accessible via 4Bh instruction - supports device authentication and secure provisioning in IoT gateways. |
Applications
| Industrial PLC Firmware Storage | Medical Device Configuration Memory |
|---|---|
|
Use Scenario: Storing boot firmware and safety-critical control algorithms in programmable logic controllers with no external RAM. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP support via Continuous Read Mode - executes directly from flash without RAM copy. Use Value: Eliminates external RAM requirement and reduces BOM cost while maintaining deterministic startup timing under –40 °C to +85 °C conditions. |
Use Scenario: Retaining calibrated sensor offsets, user preferences, and audit logs in portable diagnostic equipment. IC Role / Device Role / Timing Role: Parameter storage with hardware write protection (/WP + SRP) - prevents corruption during brown-out or ESD events. Use Value: Ensures regulatory compliance (IEC 62304) by guaranteeing parameter integrity across 100,000+ write cycles and 20-year retention. |
| Smart Meter Bootloader Image | Automotive Body Control Module NVM |
|
Use Scenario: Hosting field-upgradable bootloader images in utility smart meters deployed in unattended outdoor enclosures. IC Role / Device Role / Timing Role: Secure firmware repository with JEDEC ID (9Fh) and Manufacturer ID (EFh) - enables authenticated firmware validation pre-boot. Use Value: Supports remote OTA updates with cryptographic signature verification using unique device identity and tamper-resistant sector protection. |
Use Scenario: Storing vehicle-specific calibration tables and CAN node configuration in body control modules. IC Role / Device Role / Timing Role: Low-power NVM with <1 µA power-down current - maintains configuration during ignition-off sleep states. Use Value: Reduces parasitic drain on 12 V battery to <1 µA, extending vehicle standby time beyond ISO 16750-2 requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF021A-SSH-T | 2 M-bit density; supports 85 MHz SPI only (no dual I/O); lacks Continuous Read Mode and Unique ID. | Higher capacity but lower throughput; no XIP optimization - better suited for static data logging than boot code. | Select when >128 KB storage is needed and dual I/O/XIP are not required; verify /HOLD timing compatibility with host MCU. |
| MX25L1006EZNI-12G | 1 M-bit; supports 104 MHz dual I/O and Continuous Read Mode; includes Quad SPI (QPI) mode not present in W25X10CLZPIG TR. | Same footprint and pinout; QPI adds future upgrade path - but requires additional MCU firmware support. | Choose for design scalability: identical functionality today with optional QPI migration path; validate /WP behavior against Winbond's SRP implementation. |
Compared with AT25DF021A-SSH-T and MX25L1006EZNI-12G, the W25X10CLZPIG TR delivers optimal balance of XIP-ready throughput, hardware-protected 4 KB sectors, and ultra-low power-down current - making it the preferred choice for cost-sensitive, space-constrained industrial boot memory where deterministic startup and long-term parameter retention are critical.
Availability
W25X10CLZPIG TR is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostics, smart metering, automotive body control, and IoT edge node designs requiring stable component supply, long lifecycle assurance, and RoHS-compliant packaging.
Supply support for W25X10CLZPIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty DRAM, mobile DRAM, and serial NOR/NAND flash memory solutions for industrial, automotive, and consumer markets.
The W25X series was designed specifically for embedded code storage and parameter retention in resource-constrained systems - emphasizing low voltage operation, small footprint packaging, and robust SPI protocol compliance including dual I/O and XIP-enabling features.
FAQ
What is the maximum clock frequency supported by W25X10CLZPIG TR in dual I/O mode?
The W25X10CLZPIG TR supports up to 104 MHz SPI clock frequency. In dual I/O mode using the BBh instruction, this yields an effective data transfer rate of 208 Mbps - achieved by transferring two bits per clock cycle on IO0 and IO1 simultaneously. This specification is validated across the full –40 °C to +85 °C operating range and is documented in Section 9.6 of the official Winbond datasheet Revision G.
Does W25X10CLZPIG TR support execute-in-place (XIP) operation?
Yes, W25X10CLZPIG TR supports true XIP operation via its Continuous Read Mode, which requires only 16 clock cycles of instruction overhead to initiate memory access. This enables microcontrollers to execute code directly from the flash without copying to RAM, reducing system latency and eliminating external RAM dependency - a key feature confirmed in Section 1 and Figure 2 of the W25X10CLZPIG TR datasheet.
How does hardware write protection work on W25X10CLZPIG TR?
W25X10CLZPIG TR implements hardware write protection through coordinated use of the /WP pin and Status Register Protect (SRP) bit. When SRP = 1 and /WP is driven low, writes to the status register (including BP0/BP1/TB bits) are blocked - locking memory protection settings at power-on. This behavior is explicitly defined in Section 8.1.6 and Table on page 11 of the Winbond datasheet Revision G.
What package types are offered for W25X10CLZPIG TR?
W25X10CLZPIG TR is manufactured in two package variants: 8-pin SOIC-150-mil (package code SN) and 8-pad USON-2×3-mm (package code UX). Both share identical pinout, electrical characteristics, and timing parameters - allowing drop-in replacement between packages based on board space constraints. Package dimensions and land patterns are detailed in Sections 10.1 and 10.2 of the official datasheet.
Is W25X10CLZPIG TR compatible with standard SPI Mode 0 and Mode 3?
Yes, W25X10CLZPIG TR fully supports SPI bus operation in both Mode 0 (CPOL = 0, CPHA = 0) and Mode 3 (CPOL = 1, CPHA = 1), as specified in Section 7.1.1 of the datasheet. The device samples DI on the rising edge and outputs DO on the falling edge of CLK in both modes, ensuring interoperability with common microcontroller SPI peripherals without protocol translation.
W25X10CLZPIG TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 1Mbit
- Memory Organization:
- 128K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 800µs
- Access Time:
- -
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25X10CLZPIG TR FAQ
1.How can I place an order for W25X10CLZPIG TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25X10CLZPIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25X10CLZPIG TR reliable?
The price and inventory of W25X10CLZPIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25X10CLZPIG TR is usually 5 days.
3.What payment methods are accepted for W25X10CLZPIG TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25X10CLZPIG TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25X10CLZPIG TR?
W25X10CLZPIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25X10CLZPIG TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25X10CLZPIG TR?
For technical support, including W25X10CLZPIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25X10CLZPIG TR requirements.
6.How does Aetrix verify that W25X10CLZPIG TR is sourced from the original manufacturer or authorized distributors?
All W25X10CLZPIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25X10CLZPIG TR meets industry standards.
7.What is the process for return or replacement of W25X10CLZPIG TR?
All W25X10CLZPIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25X10CLZPIG TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25X10CLZPIG TR part is unused and in its original packaging.
Return procedure for W25X10CLZPIG TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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