Winbond Electronics Corporation W25X20VZPIG
- Part No.:
- W25X20VZPIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25X20VZPIG.pdf
- Description:
- IC FLASH 2MBIT SPI 75MHZ 8WSON
- Quantity:
- Payment:

- Shipping:

Inventory:3,958
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25X20VZPIG from Winbond is a 2M-bit (256KB) serial flash memory IC designed for embedded code storage and data logging in space-constrained systems. It supports standard and dual-output SPI interfaces, operates from 2.7V to 3.6V, delivers up to 150 Mbps effective read throughput via Fast Read Dual Output (3Bh), and features uniform 4KB sectors and 64KB blocks for flexible firmware partitioning in microcontroller boot applications.
For engineers reviewing the W25X20VZPIG datasheet, W25X20VZPIG pinout, W25X20VZPIG application, or W25X20VZPIG equivalent, key selection criteria include its 75 MHz SPI clock rating, hardware /WP and /HOLD control pins, 100,000 erase/write cycle endurance, JEDEC-compliant device ID (3012h), and support for sector/block/chip erase granularity - all critical for reliable firmware update and parameter storage designs.
Technical Context
The W25X20VZPIG implements a standard SPI interface compliant with Modes 0 and 3, with dual-output capability activated exclusively by the Fast Read Dual Output (3Bh) instruction. Its internal architecture includes a 1024-page × 256-byte array organized into 64 uniform 4KB sectors and 4 erasable 64KB blocks.
Write protection is enforced through both software (Status Register BP2–BP0, TB, SRP bits) and hardware (/WP pin), enabling selective top/bottom array locking. The /HOLD pin provides deterministic bus arbitration by pausing active operations without resetting internal state, while /CS tracking of VCC ensures robust power-up sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 2 M-bit (256 KB), mapped as 1024 pages × 256 bytes - enables full firmware image storage for mid-size MCUs. |
| Sector/Block Size | Uniform 4 KB sectors (64 total) and 64 KB blocks (4 total) - supports granular OTA updates and parameter partitioning. |
| SPI Clock Max | 75 MHz - achieves 150 Mbps effective read rate using Fast Read Dual Output (3Bh), matching parallel flash performance. |
| Endurance & Retention | 100,000 program/erase cycles; 20-year data retention - suitable for field-updatable industrial firmware. |
| Supply Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic domains and low-power battery-backed systems. |
| Operating Temp | −40 °C to +85 °C - qualified for industrial-grade embedded deployment. |
| Active/Power-down Current | 5 mA typical active; 1 µA typical power-down - minimizes standby power in always-on edge devices. |
Pinout & Package
W25X20VZPIG is packaged in an 8-contact 6×5 mm WSON (package code ZP), offering compact footprint and thermal performance for high-density PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable: must transition high→low after power-up before any instruction; controls DO high-impedance state. |
| DO | Serial Data Output | Single-output data path; shifts data on CLK falling edge; used in standard read (03h/0Bh) and status reads. |
| /WP | Write Protect Input | Hardware lock for Status Register writes when SRP=1; prevents accidental configuration changes during noise events. |
| GND | Ground Reference | Signal and power return; requires low-impedance connection to minimize SPI timing jitter and noise coupling. |
| DIO | Serial Data I/O | Bidirectional SPI data line: latches input on CLK rising edge; outputs dual-bit data during Fast Read Dual Output (3Bh). |
| CLK | Serial Clock Input | Timing reference for all SPI transfers; supports Mode 0 (CLK idle low) and Mode 3 (CLK idle high); max 75 MHz. |
| /HOLD | Hold Input | Pauses ongoing SPI operation (e.g., page program) without resetting internal state; enables multi-device bus sharing. |
| VCC | Power Supply | 2.7–3.6 V supply; requires local 0.1 µF decoupling; tracks /CS at power-up to prevent spurious writes. |
Key Features
| Feature | Design Value |
|---|---|
| Dual Output SPI Interface | Enables 150 Mbps read throughput via Fast Read Dual Output (3Bh), eliminating need for wider parallel buses in cost-sensitive designs. |
| Flexible Erase Granularity | Independent 4 KB sector erase (20h) and 64 KB block erase (D8h) allow partial firmware updates without full chip reprogramming. |
| Hardware + Software Write Protection | Combines /WP pin control with programmable BP2–BP0 and TB bits to lock top/bottom memory regions - critical for bootloader safety. |
| Low-Power Power-down Mode | 1 µA typical standby current with B9h instruction - extends battery life in portable IoT sensors and wearables. |
| JEDEC Standard Identification | Returns Manufacturer ID EFh and Device ID 3012h via ABh/90h/9Fh instructions - ensures interoperability with generic flash programming tools. |
Applications
| Firmware Boot Storage | Industrial Parameter Logging |
|---|---|
|
Use Scenario: Storing MCU boot code and initialization routines in resource-limited edge controllers. IC Role / Device Role / Timing Role: Non-volatile code storage accessed via SPI during cold start; supports fast shadowing to RAM using Fast Read Dual Output. Use Value: Reduces boot time by 2× vs. standard SPI reads; 4 KB sector alignment simplifies secure OTA update partitioning. |
Use Scenario: Recording sensor calibration data, fault logs, and operational history in factory automation PLCs. IC Role / Device Role / Timing Role: Parameter storage with atomic sector-level writes; leverages /HOLD to pause logging during interrupt-driven I/O bursts. Use Value: 100,000-cycle endurance ensures >10 years of daily logging at 27 entries/day; hardware /WP prevents corruption during brownouts. |
| Consumer Device Configuration | Medical Diagnostic Firmware |
|
Use Scenario: Holding user preferences, display themes, and connectivity settings in smart home hubs. IC Role / Device Role / Timing Role: Persistent configuration store accessed intermittently; uses Write Disable (04h) and Status Register protection to lock settings post-setup. Use Value: Top/bottom block protect (TB bit) isolates factory defaults from user-modifiable regions - prevents bricking during misconfiguration. |
Use Scenario: Storing FDA-cleared diagnostic algorithms and calibration tables in portable ultrasound units. IC Role / Device Role / Timing Role: Certified firmware repository with write-protection enforced by /WP pin and SRP bit during clinical operation. Use Value: 20-year data retention meets medical device shelf-life requirements; JEDEC ID (3012h) enables automated BOM verification in production test. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF021-SSHN-B | 2 M-bit SPI flash; 85 MHz max clock; no dual-output mode; supports 2.3–3.6 V supply. | Lacks Fast Read Dual Output - limits read bandwidth in boot-critical systems requiring <50 ms code load. | Prefer when dual-output is unnecessary and broader voltage range (2.3 V) is required for battery-depleted operation. |
| SST25VF020B-20-4I-SAE | 2 M-bit SPI flash; 20 MHz max clock; no dual-output; supports 2.7–3.6 V; 100 kHz minimum erase voltage. | Significantly lower SPI speed and no dual-output - unsuitable for real-time firmware shadowing or high-throughput logging. | Select only for legacy compatibility where existing SST25VF drivers are in use and performance is non-critical. |
Compared with AT25DF021-SSHN-B and SST25VF020B-20-4I-SAE, W25X20VZPIG delivers 3.75× higher effective read bandwidth via dual-output SPI and maintains identical 2.7–3.6 V and −40°C to +85°C operating ranges - making it the optimal choice for latency-sensitive embedded boot and logging applications.
Availability
W25X20VZPIG is available at Aetrix Electronics and suitable for industrial control firmware storage, medical device configuration management, and consumer electronics parameter logging requiring stable component supply across multi-year production cycles.
Supply support for W25X20VZPIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including serial flash, PSRAM, and mobile DRAM for embedded and communications markets.
W25X20VZPIG belongs to Winbond's W25X family of high-performance serial flash memories, engineered specifically for code execution, firmware storage, and data logging in space- and power-constrained microcontroller systems.
FAQ
What is the maximum SPI clock frequency supported by W25X20VZPIG?
W25X20VZPIG supports a maximum SPI clock frequency of 75 MHz. This enables standard read operations at up to 75 Mbps and, when using the Fast Read Dual Output (3Bh) instruction, achieves an effective data transfer rate of 150 Mbps by utilizing both DIO and DO lines simultaneously. The 75 MHz rating is specified under standard operating conditions (2.7–3.6 V, −40°C to +85°C) and verified per AC Electrical Characteristics in the official datasheet.
Does W25X20VZPIG support dual-output SPI mode, and how is it enabled?
Yes, W25X20VZPIG supports dual-output SPI exclusively via the Fast Read Dual Output instruction (0x3B). Unlike standard SPI reads (0x03 or 0x0B), this command repurposes the DIO pin as a second output during data transfer, doubling throughput. No configuration register setting is required - activation is instruction-triggered. The feature is fully documented in Section 9.1.2 of the W25X20 datasheet and requires compatible host controller firmware to issue 0x3B with proper address/dummy byte sequencing.
How many program/erase cycles does W25X20VZPIG guarantee, and what is its data retention?
W25X20VZPIG guarantees a minimum of 100,000 program/erase cycles per sector and 20 years of data retention at +25°C. These specifications are validated across the full operating temperature range (−40°C to +85°C) and published in Section 11.3 (Endurance and Data Retention) of the official datasheet. Real-world endurance may vary based on erase block usage patterns and ambient temperature profiles.
What package type is used for W25X20VZPIG, and what are its key mechanical dimensions?
W25X20VZPIG uses an 8-contact 6×5 mm WSON package (package code ZP), as confirmed in Section 12.4 of the datasheet. Its body dimensions are 6.0 mm × 5.0 mm × 0.75 mm (max height), with 0.65 mm pitch and exposed pad thermal design. This leadless package offers superior thermal dissipation and board-area efficiency compared to SOIC or PDIP variants, making it ideal for compact industrial and portable electronics.
Can W25X20VZPIG be hardware write-protected, and how does /WP interact with the Status Register?
Yes, W25X20VZPIG supports hardware write protection via the /WP pin in conjunction with the Status Register Protect (SRP) bit. When SRP = 1 and /WP is driven low, all Status Register writes (including Block Protect and Top/Bottom bits) are blocked - preventing accidental or noise-induced configuration changes. This interaction is explicitly defined in Section 10.1.6 and Figure 3 of the datasheet, and /WP remains active regardless of /CS state.
W25X20VZPIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 2Mbit
- Memory Organization:
- 256K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 75 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25X20VZPIG FAQ
1.How can I place an order for W25X20VZPIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25X20VZPIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25X20VZPIG reliable?
The price and inventory of W25X20VZPIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25X20VZPIG is usually 5 days.
3.What payment methods are accepted for W25X20VZPIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25X20VZPIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25X20VZPIG?
W25X20VZPIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25X20VZPIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25X20VZPIG?
For technical support, including W25X20VZPIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25X20VZPIG requirements.
6.How does Aetrix verify that W25X20VZPIG is sourced from the original manufacturer or authorized distributors?
All W25X20VZPIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25X20VZPIG meets industry standards.
7.What is the process for return or replacement of W25X20VZPIG?
All W25X20VZPIG units undergo pre-shipment inspection (PSI). If there is an issue with W25X20VZPIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25X20VZPIG part is unused and in its original packaging.
Return procedure for W25X20VZPIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25X20VZPIG Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
