Winbond Electronics Corporation W25X40CLSVIG TR
- Part No.:
- W25X40CLSVIG TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
W25X40CLSVIG TR.pdf
- Description:
- IC FLASH 4MBIT SPI 104MHZ 8VSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,472
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25X40CLSVIG TR from Winbond is a 4 M-bit (512 KB) serial flash memory IC designed for embedded code storage and data logging in space-constrained systems. It supports standard SPI, dual-output SPI, and dual I/O SPI interfaces; operates from 2.3 V to 3.6 V; delivers up to 208 Mbps effective throughput via Fast Read Dual I/O (BBh); and features uniform 4 KB sectors, 32 KB blocks, and 64 KB blocks for flexible firmware partitioning in microcontroller boot applications.
For engineers reviewing the W25X40CLSVIG TR datasheet, W25X40CLSVIG TR pinout, W25X40CLSVIG TR application, or W25X40CLSVIG TR equivalent, key selection considerations include its 8-pin SOIC 150-mil (SN) package, 104 MHz max SPI clock, hardware /WP and /HOLD pins for system-level control, and JEDEC-compliant manufacturer/device ID (EFh/12h) for automated BOM verification.
Technical Context
The W25X40CLSVIG TR implements a SPI-compatible command-set architecture with volatile write-enable latch (WEL) and non-volatile status register (SRP, BP2–BP0, TB) for granular hardware/software write protection. Its dual I/O mode uses bidirectional IO0/IO1 pins under BBh instruction, enabling true XIP-capable continuous read with ≤16-clock address overhead.
Internally organized as 2048 × 256-byte pages across 128 × 4 KB sectors, it supports page program (<1 ms), sector/32KB/64KB/block erase, and chip erase - all with >100,000 endurance cycles and >20-year data retention at -40°C to +85°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 4 M-bit (512 KB), organized as 2048 pages × 256 bytes |
| Sector Architecture | 128 uniform 4 KB sectors; 16 × 32 KB blocks; 8 × 64 KB blocks |
| Max SPI Clock | 104 MHz - enables 208 Mbps effective bandwidth in Dual I/O mode (BBh) |
| Supply Voltage | 2.3 V to 3.6 V - compatible with 2.5 V, 3.0 V, and 3.3 V logic domains |
| Active/Power-down Current | 1 mA typical active; <1 µA typical power-down - suitable for battery-backed systems |
| Endurance & Retention | >100,000 program/erase cycles; >20 years data retention at +85°C |
| Operating Temperature | -40°C to +85°C - industrial-grade qualification for embedded deployment |
Pinout & Package
W25X40CLSVIG TR is packaged in an 8-pin SOIC 150-mil (package code SN), with gull-wing leads, 1.27 mm pitch, and JEDEC MS-012AC compliant footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable: high = device deselected (DO high-Z, standby current); low = selected (active current, accepts instructions) |
| 2 DO (IO1) | Serial Data Output / Dual I/O | Standard SPI output (falling-edge CLK); becomes bidirectional IO1 in Dual SPI modes (3Bh/BBh) |
| 3 /WP | Write Protect Input | Hardware lock: low = prevents Status Register writes when SRP=1; supports top/bottom array protection |
| 4 GND | Ground Reference | Signal and power return path; must be low-impedance for stable SPI timing and noise immunity |
| 5 DI (IO0) | Serial Data Input / Dual I/O | Standard SPI input (rising-edge CLK); becomes bidirectional IO0 in Dual SPI modes (3Bh/BBh) |
| 6 CLK | Serial Clock Input | Master-generated timing signal; supports SPI Modes 0 and 3; max 104 MHz frequency |
| 7 /HOLD | Hold Input | Pauses ongoing SPI transaction while /CS remains low; enables multi-device bus sharing without reset |
| 8 VCC | Power Supply | 2.3–3.6 V single supply; internal charge pump generates programming voltage; requires local 0.1 µF decoupling |
Key Features
| Feature | Design Value |
|---|---|
| Dual I/O SPI Interface | Enables BBh instruction for 2× throughput vs standard SPI - critical for fast boot code shadowing |
| Continuous Read Mode | Reduces instruction overhead to ≤16 clocks per 24-bit address - supports true execute-in-place (XIP) operation |
| Hardware + Software Write Protection | Combines /WP pin, SRP bit, and BP2–BP0/TB bits to protect 4 KB–entire array without firmware intervention |
| Uniform Erase Granularity | 4 KB sectors allow fine-grained firmware updates without erasing unrelated configuration or calibration data |
| JEDEC ID & Unique Serial Number | Factory-programmed 64-bit UID and EFh/12h ID enable automated BOM traceability and secure device authentication |
Applications
| Firmware Boot Storage | IoT Edge Device Logging |
|---|---|
|
Use Scenario: Storing bootloader and application firmware for ARM Cortex-M microcontrollers in compact consumer electronics. IC Role / Device Role / Timing Role: Non-volatile code storage accessed via SPI during cold start; supports XIP for latency-sensitive initialization. Use Value: 4 KB sector granularity enables atomic firmware patching; 104 MHz Dual I/O reduces boot time by >40% vs legacy 40 MHz SPI flash. |
Use Scenario: Capturing sensor telemetry and event logs in battery-powered smart meters with infrequent write cycles. IC Role / Device Role / Timing Role: Parameter/data storage with wear-leveling-friendly erase boundaries and ultra-low power-down current (<1 µA). Use Value: >100,000 endurance cycles ensure >10-year field life at 10 writes/day; hardware /WP prevents corruption during brown-out events. |
| Industrial HMI Configuration | Medical Device Calibration Data |
|
Use Scenario: Holding UI assets, language packs, and user preferences in panel-mounted HMIs operating across wide temperature ranges. IC Role / Device Role / Timing Role: Persistent storage for non-volatile settings; accessed via standard SPI during GUI initialization. Use Value: -40°C to +85°C rating ensures reliability in uncontrolled environments; TB/BP bits lock factory calibration against accidental overwrite. |
Use Scenario: Securing sensor calibration coefficients and regulatory audit trails in Class II medical instruments requiring data integrity. IC Role / Device Role / Timing Role: Tamper-resistant storage with hardware-enforced write protection and unique device identification. Use Value: /WP + SRP + BP bits provide three-layer protection; 64-bit UID enables per-unit calibration traceability per FDA 21 CFR Part 11. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT25DF041A-SSHN-B | 4 M-bit, 3.3 V only, max 85 MHz SPI clock, no Dual I/O support, 2.7–3.6 V range | Lacks BBh instruction and XIP-optimized continuous read - unsuitable for high-speed boot or real-time code execution | Select only if Dual I/O and >100 MHz timing are unnecessary and legacy Atmel toolchain compatibility is required. |
| MX25L4005AM1I-12G | 4 M-bit, 2.7–3.6 V, supports Dual I/O (BBh), 80 MHz max clock, same 4 KB sector layout | Lower max clock limits sustained throughput to ~160 Mbps; lacks 64-bit UID but offers identical protection scheme | Prefer when cost sensitivity outweighs 25% bandwidth advantage and UID-based traceability is not mandated. |
Compared with AT25DF041A-SSHN-B and MX25L4005AM1I-12G, the W25X40CLSVIG TR delivers highest effective bandwidth (208 Mbps), widest voltage range (2.3–3.6 V), and unique device identification - making it optimal for next-generation embedded systems demanding speed, flexibility, and traceability.
Availability
W25X40CLSVIG TR is available at Aetrix Electronics and suitable for firmware boot storage, IoT edge device logging, and industrial HMI configuration requiring stable component supply, long-term lifecycle assurance, and full industrial temperature compliance.
Supply support for W25X40CLSVIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial flash, PSRAM, and mobile DRAM, serving automotive, industrial, and computing markets since 1987.
The W25X series was engineered for embedded systems needing high-speed, low-power, and pin-efficient non-volatile storage - specifically targeting MCU boot code, parameter retention, and firmware update resilience in resource-constrained designs.
FAQ
What is the maximum SPI clock frequency supported by the W25X40CLSVIG TR?
The W25X40CLSVIG TR supports a maximum SPI clock frequency of 104 MHz. This enables standard SPI transfers at 104 Mbps and, when using Fast Read Dual I/O (BBh) instruction, achieves an effective throughput of 208 Mbps. The device maintains timing compliance across its full industrial temperature range (-40°C to +85°C) and 2.3–3.6 V supply window, making W25X40CLSVIG TR suitable for high-performance boot and code-shadowing applications where latency matters.
Does the W25X40CLSVIG TR support execute-in-place (XIP) operation?
Yes, the W25X40CLSVIG TR supports true XIP via its Continuous Read Mode, which reduces instruction overhead to as few as 16 clock cycles for addressing - enabling efficient sequential instruction fetch directly over SPI. This capability is validated under Fast Read Dual Output (3Bh) and Fast Read Dual I/O (BBh) commands, and W25X40CLSVIG TR's uniform 4 KB sector architecture ensures safe, atomic firmware updates without disrupting executing code regions.
How does hardware write protection work on the W25X40CLSVIG TR?
Hardware write protection on the W25X40CLSVIG TR combines the /WP pin with non-volatile status register bits (SRP, BP2–BP0, TB). When SRP = 1 and /WP is low, Status Register writes are blocked; BP/TB bits then define protected memory regions - from individual 4 KB sectors up to the full 512 KB array. This dual-layer scheme ensures W25X40CLSVIG TR remains immune to accidental writes during power transients or software faults, even if firmware fails to issue Write Disable.
What package type is used for the W25X40CLSVIG TR?
The W25X40CLSVIG TR uses an 8-pin SOIC 150-mil package (package code SN), measuring 3.9 mm × 4.9 mm with 1.27 mm lead pitch and gull-wing leads. It is JEDEC MS-012AC compliant, pin-compatible with other W25X-series variants in SOIC 150-mil, and optimized for reflow soldering in high-volume SMT assembly. This package balances board space efficiency, thermal performance, and test accessibility for W25X40CLSVIG TR integration.
Can the W25X40CLSVIG TR be used in automotive applications?
The W25X40CLSVIG TR is rated for -40°C to +85°C operation and meets industrial reliability standards (e.g., >100,000 endurance cycles, >20-year data retention), but it is not AEC-Q100 qualified. For automotive applications requiring qualification, Winbond offers the pin-compatible W25Q40EW variant. While W25X40CLSVIG TR may function in cabin-temperature zones, designers must validate EMI robustness, transient immunity, and long-term reliability per ISO/TS 16949 before deploying W25X40CLSVIG TR in safety-critical or under-hood automotive systems.
W25X40CLSVIG TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH
- Memory Size:
- 4Mbit
- Memory Organization:
- 512K x 8
- Memory Interface:
- SPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 800µs
- Access Time:
- -
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSOP
W25X40CLSVIG TR FAQ
1.How can I place an order for W25X40CLSVIG TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25X40CLSVIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25X40CLSVIG TR reliable?
The price and inventory of W25X40CLSVIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25X40CLSVIG TR is usually 5 days.
3.What payment methods are accepted for W25X40CLSVIG TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25X40CLSVIG TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25X40CLSVIG TR?
W25X40CLSVIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25X40CLSVIG TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25X40CLSVIG TR?
For technical support, including W25X40CLSVIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25X40CLSVIG TR requirements.
6.How does Aetrix verify that W25X40CLSVIG TR is sourced from the original manufacturer or authorized distributors?
All W25X40CLSVIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25X40CLSVIG TR meets industry standards.
7.What is the process for return or replacement of W25X40CLSVIG TR?
All W25X40CLSVIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25X40CLSVIG TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25X40CLSVIG TR part is unused and in its original packaging.
Return procedure for W25X40CLSVIG TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25X40CLSVIG TR Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

