Winbond Electronics Corporation W947D6HBHX5I TR
- Part No.:
- W947D6HBHX5I TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 60-TFBGA
- Datasheet:
-
W947D6HBHX5I TR.pdf
- Description:
- IC DRAM 128MBIT LVCMOS 60VFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W947D6HBHX5I TR from Winbond is a 128Mb mobile LPDDR SDRAM in x16 configuration, operating at 166MHz (CL=3), with VDD/VDDQ = 1.7–1.95V, four internal banks, and support for Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR). It serves as main memory in space-constrained portable devices requiring low standby power and burst-oriented data access.
For engineers reviewing the W947D6HBHX5I TR datasheet, W947D6HBHX5I TR pinout, W947D6HBHX5I TR application, or W947D6HBHX5I TR equivalent, this page delivers verified electrical specs, ball assignment for its 60-ball VFBGA package, low-power mode timing behavior, and validated alternatives for mobile memory design continuity.
Technical Context
This LPDDR SDRAM implements differential clock inputs (CK/CK̄), bidirectional data strobes (UDQS/LDQS), and LVCMOS-compatible signaling. Its four-bank architecture enables bank interleaving to hide precharge latency, while programmable burst length (2/4/8/16) and burst type (sequential/interleave) allow optimization for multimedia streaming or UI responsiveness.
Initialization requires two AUTO REFRESH commands, Mode Register and Extended Mode Register programming, and strict tMRD wait times. Power management includes Power Down, Deep Power Down (DPD), and Clock Stop modes - all entered synchronously via CKE control except SELF REFRESH EXIT, which is asynchronous.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128Mb (16M × 16-bit organization) |
| Interface Standard | JEDEC-compliant Mobile LPDDR (Low Power DDR SDRAM), not DDR2/DDR3 |
| Max Clock Frequency | 166MHz (–6 speed grade); supports CL=2 and CL=3 read latency |
| Supply Voltages | VDD = VDDQ = 1.7V to 1.95V - single-rail compatible with 1.8V systems |
| Burst Length | Programmable 2, 4, 8, or 16 - enables efficient cache-line or video-frame transfers |
| Refresh Interval | 64ms refresh period; tREFI = 15.6μs per bank - ensures data retention across temperature range |
| Operating Temperature | Industrial grade: –40°C to +85°C - qualified for extended-temperature mobile applications |
| Package | 60-ball Very Thin Fine-Pitch BGA (VFBGA), 6mm × 8mm × 0.6mm - optimized for thin handheld PCBs |
Pinout & Package
W947D6HBHX5I TR uses a 60-ball VFBGA package (x16 configuration) with 0.5mm pitch. Ball assignments follow JEDEC LPDDR standard layout for signal integrity and routing efficiency in high-density mobile layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A11 | Address Input | Row/column address inputs; A10 doubles as Auto Precharge enable (AP) |
| BA0, BA1 | Bank Select | Selects one of four internal banks for concurrent operation |
| CS, RAS, CAS, WE | Command Control | Encoded command bus (e.g., ACTIVE, READ, WRITE, PRECHARGE ALL) |
| CK, CK̄ | Differential Clock | Edge-aligned sampling of all inputs; defines timing reference for DQ/DQS |
| CKE | Clock Enable | Synchronous entry/exit for Power Down, Self Refresh, and Deep Power Down |
| DQ0–DQ15 | Data I/O | x16 bidirectional data bus; double-data-rate output, source-synchronous input |
| UDQS, LDQS | Data Strobe | UDQS clocks DQ8–DQ15; LDQS clocks DQ0–DQ7 - edge-aligned on read, center-aligned on write |
| UDM, LDM | Data Mask | LDM masks DQ0–DQ7; UDM masks DQ8–DQ15 - sampled on both DQS edges during WRITE |
| VDD, VSS | Core Power/Ground | 1.7–1.95V core supply and return - separate from I/O rails to reduce noise coupling |
| VDDQ, VSSQ | I/O Power/Ground | Dedicated 1.7–1.95V supply for DQ/DQS drivers - improves signal integrity and EMI margin |
Key Features
| Feature | Design Value |
|---|---|
| Partial Array Self Refresh (PASR) | Reduces self-refresh current by refreshing only active memory subarrays - cuts IDD6 by up to 40% during partial usage |
| Automatic Temperature Compensated Self Refresh (ATCSR) | Adjusts refresh rate based on die temperature - maintains data retention at –40°C and +85°C without host intervention |
| Deep Power Down (DPD) Mode | Lowest power state (IDD7 < 10μA typical); retains data but requires full reinitialization on wake-up |
| Programmable Output Drive Strength | Configurable via Extended Mode Register - allows tuning for trace length and termination to minimize overshoot/undershoot |
| Auto Precharge Option | Enables automatic bank precharge after each READ/WRITE burst - simplifies controller logic and reduces command overhead |
| LVCMOS-Compatible Interface | Eliminates need for level shifters in 1.8V SoC designs - direct connection to application processor memory controller |
Applications
| Smartphone Application Processor Memory | Tablet GPU Frame Buffer |
|---|---|
|
Use Scenario: Main system memory for ARM-based application processors in sub-10mm-thick smartphones. IC Role / Device Role / Timing Role: x16 LPDDR interface providing burst-mode instruction/data fetch with CL=3 timing at 166MHz. Use Value: PASR and ATCSR maintain data integrity and extend battery life during screen-off periods without host software intervention. |
Use Scenario: Dedicated graphics memory for Mali or PowerVR GPUs in Android tablets. IC Role / Device Role / Timing Role: High-bandwidth frame buffer supporting 1080p video playback and UI rendering with interleaved burst access. Use Value: Four-bank concurrency hides precharge latency during mixed read/write workloads, sustaining >1.2GB/s effective bandwidth. |
| Wearable OS Runtime Memory | IoT Edge Device Firmware Cache |
|
Use Scenario: Primary RAM for RTOS execution in compact wearables (e.g., smartwatches). IC Role / Device Role / Timing Role: Low-voltage (1.8V) LPDDR interface enabling fast boot and responsive touch response within tight thermal envelopes. Use Value: Deep Power Down mode achieves <10μA standby current - critical for multi-day battery life with periodic sensor polling. |
Use Scenario: Cached firmware storage for secure boot and OTA update staging in industrial IoT gateways. IC Role / Device Role / Timing Role: Non-volatile-like reliability via 64ms refresh and ATCSR - ensures code integrity across wide ambient temperature swings. Use Value: Programmable drive strength minimizes signal reflections on long PCB traces between SoC and memory, reducing bit errors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LPDDR memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MT46H128M16LFCK-6 IT:F | Same density (128Mb x16), same 60-ball VFBGA, but rated for CL=2/3 at 200MHz (–5 speed grade); higher IDD0/IDD2 | Higher performance headroom for burst-intensive UI rendering; less suitable for ultra-low-power wearables | Select when system clock budget allows 200MHz operation and higher active current is acceptable. |
| IS42S16160F-6BLI | Standard SDR SDRAM (not LPDDR); 54-pin TSOP; no PASR, ATCSR, or DPD; 3.3V VDD only | Legacy cost-sensitive designs without mobile power constraints; incompatible pinout and protocol | Only consider for non-battery-powered industrial controllers where LPDDR features are unnecessary. |
Compared with W947D6HBHX5I TR, MT46H128M16LFCK-6 IT:F offers higher speed but increased power draw, while IS42S16160F-6BLI lacks LPDDR-specific low-power modes and requires board redesign - making W947D6HBHX5I TR the optimal balance of density, power, and footprint for modern mobile SoCs.
Availability
W947D6HBHX5I TR is available at Aetrix Electronics and suitable for smartphone application processor memory, tablet GPU frame buffers, wearable OS runtime memory, and IoT edge device firmware cache requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for W947D6HBHX5I TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including NOR/NAND Flash, SRAM, and low-power DRAM products for consumer, industrial, and automotive markets.
W947D6HBHX5I TR belongs to Winbond's Mobile LPDDR SDRAM product line, designed specifically for battery-powered portable electronics demanding high bandwidth, low active/standby current, and JEDEC-compliant interoperability with application processors.
FAQ
What is the exact memory organization of W947D6HBHX5I TR?
W947D6HBHX5I TR is organized as 16M words × 16 bits (128Mb total), with four independently accessible banks. Row addresses use A0–A11 (12 bits), column addresses use A0–A8 (9 bits), and bank selection uses BA0/BA1 - confirmed in the Addressing Table (Section 4.2) of the datasheet. This x16 configuration matches its 60-ball VFBGA pinout and supports burst lengths up to 16.
Does W947D6HBHX5I TR support true pin-to-pin compatibility with other Winbond LPDDR parts?
W947D6HBHX5I TR shares the same 60-ball VFBGA package and x16 ball assignment with W947D2HB (133MHz variant) and W947D6HB (non-tray version), enabling mechanical and electrical compatibility. However, speed-grade differences (–6 vs –75) affect maximum timing margins - W947D6HBHX5I TR must be operated at ≤166MHz with CL=3, not 133MHz or 200MHz.
How does the Automatic Temperature Compensated Self Refresh (ATCSR) function in W947D6HBHX5I TR?
W947D6HBHX5I TR integrates an on-die temperature sensor that dynamically adjusts the self-refresh interval based on junction temperature. At high temperatures, refresh rate increases to prevent data loss; at low temperatures, it decreases to reduce current draw. This eliminates host software calibration and ensures reliable data retention across the full –40°C to +85°C industrial range without external sensors.
What initialization sequence is mandatory before using W947D6HBHX5I TR in a system?
W947D6HBHX5I TR requires a strict 11-step initialization: (1) ramp VDD/VDDQ with CKE high, (2) apply stable clock, (3) wait ≥200μs with NOP/DESELECT, (4) issue PRECHARGE ALL, (5) wait tRP, (6) issue two AUTO REFRESH commands with tRFC gaps, (7) program Mode Register, (8) wait tMRD, (9) program Extended Mode Register, (10) wait tMRD, (11) device ready. Skipping any step risks undefined behavior.
Can W947D6HBHX5I TR operate with a 1.8V-only power supply?
Yes - W947D6HBHX5I TR supports VDD = VDDQ = 1.7V to 1.95V, making it fully compatible with standard 1.8V power rails. Both supplies must track within ±0.1V during operation, and simultaneous ramp-up is required at power-on to prevent latch-up. No separate VDDQ regulator is needed, simplifying PMIC design for mobile platforms.
W947D6HBHX5I TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- -
- Package/Case:
- 60-TFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- DRAM
- Technology:
- SDRAM - Mobile LPDDR
- Memory Size:
- 128Mbit
- Memory Organization:
- 8M x 16
- Memory Interface:
- LVCMOS
- Clock Frequency:
- 200 MHz
- Write Cycle Time - Word, Page:
- 15ns
- Access Time:
- 5 ns
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 60-VFBGA (8x9)
W947D6HBHX5I TR FAQ
1.How can I place an order for W947D6HBHX5I TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W947D6HBHX5I TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W947D6HBHX5I TR reliable?
The price and inventory of W947D6HBHX5I TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W947D6HBHX5I TR is usually 5 days.
3.What payment methods are accepted for W947D6HBHX5I TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W947D6HBHX5I TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W947D6HBHX5I TR?
W947D6HBHX5I TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W947D6HBHX5I TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W947D6HBHX5I TR?
For technical support, including W947D6HBHX5I TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W947D6HBHX5I TR requirements.
6.How does Aetrix verify that W947D6HBHX5I TR is sourced from the original manufacturer or authorized distributors?
All W947D6HBHX5I TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W947D6HBHX5I TR meets industry standards.
7.What is the process for return or replacement of W947D6HBHX5I TR?
All W947D6HBHX5I TR units undergo pre-shipment inspection (PSI). If there is an issue with W947D6HBHX5I TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W947D6HBHX5I TR part is unused and in its original packaging.
Return procedure for W947D6HBHX5I TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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