My Inquiry
My Account
Winbond Electronics Corporation W987D2HBJX6I TR
- Part No.:
- W987D2HBJX6I TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 90-TFBGA
- Datasheet:
-
W987D2HBJX6I TR.pdf
- Description:
- IC DRAM 128MBIT PAR 90VFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,528
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W987D2HBJX6I TR from Winbond is a 128Mb mobile low-power SDRAM (LPSDR) in x16 organization, operating at 1.8V with 166MHz clock rate (CL=3), supporting CAS latency 2/3, burst lengths 1–8, and 4K refresh/64ms. It delivers synchronized data on positive clock edges and targets battery-powered handheld systems requiring high-density memory with ultra-low standby current (0.23mA in power-down mode).
For engineers reviewing the W987D2HBJX6I TR datasheet, W987D2HBJX6I TR pinout, W987D2HBJX6I TR application, or W987D2HBJX6I TR equivalent, key selection criteria include its VFBGA-54 package, LVCMOS 1.8V interface, Automatic Temperature Compensated Self Refresh (ATCSR), Partial Array Self Refresh (PASR), and Deep Power Down Mode for mobile SoC memory subsystems.
Technical Context
This LPSDR implements a synchronous command interface with four internal banks, row/column address multiplexing via A0–A11 and BA0/BA1, and supports full-page, sequential, and interleaved burst modes. Its control logic decodes RAS/CAS/WE/CKE/CS commands on CLK rising edges to execute bank activate, precharge, read/write, auto-refresh, and self-refresh entry/exit operations.
The device integrates on-die temperature-compensated refresh counters and programmable output driver strength, enabling dynamic power optimization across operating temperatures (−40°C to +85°C). It uses separate VDDQ/VSSQ rails for I/O buffers to reduce noise coupling and supports both normal and low-power power-down modes with distinct current profiles.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128Mb (2,097,152 words × 4 banks × 16 bits) |
| Supply Voltage | VDD = VDDQ = 1.7V–1.95V - enables single-rail 1.8V system integration with LVCMOS compatibility |
| Max Clock Frequency | 166MHz (tCK = 6ns, CL=3) - defines peak data throughput of 2.656 Gb/s in burst mode |
| CAS Latency | Programmable CL=2 or CL=3 - determines read access timing overhead and system timing margin requirements |
| Refresh Rate | 4K cycles / 64ms - mandates minimum refresh command interval of 15.625μs per bank |
| Power-Down Current | 0.23mA (low-power mode) - critical for extending battery life during display-off or idle states |
| Package | 54-ball VFBGA (x16), 6.0mm × 8.0mm × 0.6mm - compact footprint for space-constrained mobile PCBs |
| Operating Temp | −40°C to +85°C (industrial grade) - qualified for sustained operation in handheld thermal environments |
Pinout & Package
W987D2HBJX6I TR uses a 54-ball Very Thin Fine-Pitch Ball Grid Array (VFBGA) package optimized for mobile applications. Pin assignments follow JEDEC-standard LPSDR x16 ballout with dedicated VDD/VSS and VDDQ/VSSQ power/ground pairs for signal integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A11 | Address Input | Multiplexed row/column address lines; A10 controls auto-precharge enable |
| BA0, BA1 | Bank Address | Selects one of four internal banks during row activation or column access |
| DQ0–DQ15 | Data I/O | 16-bit bidirectional data bus with DQM-controlled masking and Hi-Z output control |
| UDQM, LDQM | Data Mask | Upper/lower byte mask signals - block write data or force Hi-Z on read outputs |
| CLK, CKE | Timing Control | System clock input and clock enable - CKE LOW enters power-down/self-refresh modes |
| CS, RAS, CAS, WE | Command Decode | Chip select and strobe inputs that define all operations (activate, read, write, refresh, etc.) |
| VDD, VSS | Core Power/Ground | 1.8V supply and return for internal logic and address buffers |
| VDDQ, VSSQ | I/O Power/Ground | Isolated 1.8V rail for DQ/DQM drivers - minimizes switching noise coupling to core logic |
Key Features
| Feature | Design Value |
|---|---|
| Automatic Temperature Compensated Self Refresh (ATCSR) | Reduces self-refresh current by up to 30% at 45°C vs. fixed-rate refresh - extends battery runtime in variable-temperature use cases |
| Partial Array Self Refresh (PASR) | Allows refresh of only 1/4 or 1/2 array - cuts IDD6 current to 150μA (full array: 180μA @45°C) when partial memory retention suffices |
| Deep Power Down Mode (DPD) | Draws only 10μA - enables multi-week standby without recharge in always-on IoT or alarm-clock applications |
| Programmable Output Driver Strength | Adjusts DQ slew rate and drive level to match trace impedance - reduces EMI and improves signal integrity on flexible PCB layouts |
| LVCMOS 1.8V Interface Compliance | Meets VIH ≥ 0.8×VDDQ and VOL ≤ 0.2V - ensures interoperability with 1.8V application processors and PMICs |
Applications
| Smartphone Baseband Memory | Digital Still Camera Buffer |
|---|---|
Use Scenario: Stores frame buffers and image processing scratchpad during burst capture and JPEG encoding in sub-200g portable cameras. IC Role / Device Role / Timing Role: Mobile LPSDR acting as primary working memory for ISP pipeline - accepts burst writes from sensor and burst reads for compression engine. Use Value: 0.23mA power-down current extends capture session time between charges; ATCSR maintains refresh accuracy across lens-heated PCB zones. |
Use Scenario: Holds preview frames and compressed JPEGs in smartphone camera subsystems with tight thermal envelopes. IC Role / Device Role / Timing Role: Low-voltage synchronous DRAM interfacing directly to ARM Cortex-A series application processor memory controller. Use Value: VFBGA-54 package fits under camera module; PASR reduces active refresh load during viewfinder-only operation. |
| Portable Gaming Console RAM | Industrial Handheld Terminal Memory |
Use Scenario: Provides game state storage and texture cache for ARM-based portable gaming devices with 4–6 hour battery life targets. IC Role / Device Role / Timing Role: High-bandwidth memory subsystem component - sustains 166MHz burst transfers during GPU rendering and audio playback. Use Value: CL=3 timing enables predictable 5.4ns tAC access; DQM masking supports partial writes without bus turnaround overhead. |
Use Scenario: Serves as main program/data memory in ruggedized barcode scanners and field service terminals operating at −25°C to +70°C ambient. IC Role / Device Role / Timing Role: Industrial-grade mobile SDRAM - withstands repeated thermal cycling and mechanical shock while maintaining 4K/64ms refresh compliance. Use Value: −40°C to +85°C rating ensures reliability in unheated warehouses; Deep Power Down preserves firmware state during overnight shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-power mobile SDRAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISSI IS42S16160J-6BLI | Same 128Mb x16 density, 166MHz, but lacks ATCSR and PASR; uses standard 54-ball FBGA | No on-die temperature compensation - requires external thermal management for refresh tuning | Choose when cost sensitivity outweighs battery-life optimization in consumer-grade designs |
| Winbond W987D2HBGX6I | Identical electrical specs and pinout, but in 90-ball VFBGA (x32) package - not pin-compatible | Supports wider 32-bit bus width - requires PCB redesign and memory controller reconfiguration | Select only if migrating to higher bandwidth and can revise layout and firmware initialization sequence |
Compared with W987D2HBJX6I TR, IS42S16160J-6BLI offers lower unit cost but forfeits ATCSR-driven power savings, while W987D2HBGX6I provides double bandwidth at the expense of board-level compatibility - making W987D2HBJX6I TR optimal for drop-in upgrades in existing x16 mobile platforms.
Availability
W987D2HBJX6I TR is available at Aetrix Electronics and suitable for smartphone baseband memory, digital still camera buffer, portable gaming console RAM, industrial handheld terminal memory, and medical point-of-care device storage requiring stable component supply across extended product lifecycles.
Supply support for W987D2HBJX6I TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory and microcontrollers, with over 30 years of DRAM design heritage and ISO/TS 16949-certified manufacturing.
W987D2HBJX6I TR belongs to Winbond's Mobile LPSDR product line, engineered specifically for battery-operated handheld devices where milliamp-level standby current, thermal-aware refresh, and ultra-thin packaging are non-negotiable system requirements.
FAQ
What is the maximum operating frequency and CAS latency supported by W987D2HBJX6I TR?
W987D2HBJX6I TR supports a maximum clock frequency of 166MHz with CAS latency 3 (tCK = 6ns), and also operates at 133MHz with CAS latency 2 (tCK = 12ns). These settings are configured via the mode register during initialization, and the -6 speed grade suffix in W987D2HBJX6I TR confirms its 166MHz capability. The device does not support CL=1 or frequencies above 166MHz.
Does W987D2HBJX6I TR support automatic temperature-compensated self-refresh (ATCSR)?
Yes, W987D2HBJX6I TR implements Automatic Temperature Compensated Self Refresh (ATCSR) as a core low-power feature. It dynamically adjusts self-refresh current based on die temperature - e.g., IDD6 drops to 150μA at 45°C for full-array refresh - reducing power consumption without sacrificing data retention reliability across its −40°C to +85°C operating range.
What package type and ball count does W987D2HBJX6I TR use?
W987D2HBJX6I TR uses a 54-ball Very Thin Fine-Pitch Ball Grid Array (VFBGA) package measuring 6.0mm × 8.0mm × 0.6mm, compliant with JEDEC MO-229VAA. This x16-organized package matches the pinout defined in Section 3.1 of the datasheet and is distinct from the 90-ball VFBGA used for the x32 variant W987D6HB.
How does Partial Array Self Refresh (PASR) function in W987D2HBJX6I TR?
In W987D2HBJX6I TR, PASR allows selective refresh of only 1/4 or 1/2 of the memory array via extended mode register settings, reducing self-refresh current from 180μA (full array) to 150μA (1/4 array) at 45°C. This feature is activated after initialization and is particularly valuable during UI-idle or sensor-sleep states where full memory retention is unnecessary.
What are the power supply requirements for W987D2HBJX6I TR?
W987D2HBJX6I TR requires two independent 1.8V supplies: VDD (1.7V–1.95V) for core logic and address buffers, and VDDQ (1.7V–1.95V) for I/O drivers. Separate VSS and VSSQ grounds are mandatory. The device draws 0.23mA in low-power power-down mode and 75mA during burst-mode operation at 166MHz - values confirmed in Section 6.4 of the datasheet.
W987D2HBJX6I TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- -
- Package/Case:
- 90-TFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- DRAM
- Technology:
- SDRAM - Mobile LPSDR
- Memory Size:
- 128Mbit
- Memory Organization:
- 4M x 32
- Memory Interface:
- Parallel
- Clock Frequency:
- 166 MHz
- Write Cycle Time - Word, Page:
- 15ns
- Access Time:
- 5.4 ns
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 90-VFBGA (8x13)
W987D2HBJX6I TR FAQ
1.How can I place an order for W987D2HBJX6I TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W987D2HBJX6I TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W987D2HBJX6I TR reliable?
The price and inventory of W987D2HBJX6I TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W987D2HBJX6I TR is usually 5 days.
3.What payment methods are accepted for W987D2HBJX6I TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W987D2HBJX6I TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W987D2HBJX6I TR?
W987D2HBJX6I TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W987D2HBJX6I TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W987D2HBJX6I TR?
For technical support, including W987D2HBJX6I TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W987D2HBJX6I TR requirements.
6.How does Aetrix verify that W987D2HBJX6I TR is sourced from the original manufacturer or authorized distributors?
All W987D2HBJX6I TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W987D2HBJX6I TR meets industry standards.
7.What is the process for return or replacement of W987D2HBJX6I TR?
All W987D2HBJX6I TR units undergo pre-shipment inspection (PSI). If there is an issue with W987D2HBJX6I TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W987D2HBJX6I TR part is unused and in its original packaging.
Return procedure for W987D2HBJX6I TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W987D2HBJX6I TR Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
