Renesas X28HC256JZ-90T1
- Part No.:
- X28HC256JZ-90T1
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
X28HC256JZ-90T1.pdf
- Description:
- IC EEPROM 256KBIT PAR 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:2,939
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X28HC256JZ-90T1 from Intersil is a 256 kbit (32k × 8), 5V-only, byte-alterable CMOS EEPROM with 90 ns access time, fabricated using textured poly floating gate technology. It supports 128-byte page writes (≤0.8 s full rewrite), DATA polling and Toggle bit write completion detection, and JEDEC-standard software data protection. It is used in industrial control systems for nonvolatile parameter storage requiring high reliability and single-supply operation.
For engineers reviewing the X28HC256JZ-90T1 datasheet, X28HC256JZ-90T1 pinout, X28HC256JZ-90T1 application, or X28HC256JZ-90T1 equivalent, key selection considerations include 90 ns read timing, 5V-only operation without high-voltage programming, 100,000 write endurance, RoHS-compliant PLCC-32 packaging, and support for early write-cycle termination via I/O6/I/O7 status bits.
Technical Context
The X28HC256JZ-90T1 implements a two-line control architecture (CE + OE for reads; CE + WE for writes) to eliminate bus contention in multi-device memory arrays. Its Direct Write™ cell structure enables self-timed internal programming without erase-before-write or external high-voltage circuitry.
It features dual write-status signaling: DATA polling on I/O7 (complement-read behavior) and Toggle bit on I/O6 (state alternation during programming). Hardware protection includes VCC sense (write inhibit below ~3.5 V) and signal-level inhibition (OE low / WE high / CE high).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory capacity | 256 kbit (32,768 × 8-bit words); sufficient for firmware configuration tables or calibration data in embedded controllers. |
| Access time | 90 ns max; enables direct interface with 10 MHz microcontrollers without wait states. |
| Write endurance | 100,000 cycles per byte; supports frequent field-updatable parameters in industrial HMI or sensor nodes. |
| Data retention | 100 years at +25°C; ensures long-term validity of stored calibration or security keys without refresh. |
| Supply voltage | 5 V ±10%; compatible with legacy 5V logic families and eliminates need for auxiliary voltage rails. |
| Operating temperature | 0°C to +70°C; qualified for commercial-grade applications including point-of-sale terminals and test equipment. |
| Power consumption | 60 mA active / 500 µA standby; reduces thermal load in dense memory arrays and extends battery backup runtime. |
Pinout & Package
Package: 32-lead Plastic Leaded Chip Carrier (PLCC), RoHS-compliant, dimensions per JEDEC MS-016AE (N32.45x55).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A14 | Address inputs | 15-bit address bus selecting one of 32,768 bytes; A7–A14 define page address for 128-byte page writes. |
| I/O0–I/O7 | Data input/output | Bidirectional 8-bit data bus; I/O7 provides DATA polling status; I/O6 provides Toggle bit status. |
| CE | Chip Enable | Active-low device select; must be LOW for all read/write operations; controls power-down entry when HIGH. |
| OE | Output Enable | Active-low output buffer control; used with CE to initiate reads; HIGH disables outputs to prevent bus contention. |
| WE | Write Enable | Active-low write strobe; latches data on rising edge; initiates byte or page write when CE is also LOW. |
| VCC | Power supply | +5 V supply; powers core logic and EEPROM array; requires local 0.1 µF ceramic decoupling. |
| VSS | Ground | Reference ground for all signals and internal circuitry; must be low-impedance connection. |
| NC | No Connect | Pins 1, 12, 17, 26 are unconnected; must remain floating-no routing or soldering permitted. |
Key Features
| Feature | Design Value |
|---|---|
| 90 ns access time | Enables zero-wait-state interfacing with 10 MHz microcontrollers and avoids timing margin compromises in real-time systems. |
| 128-byte page write | Reduces full-memory rewrite time to ≤0.8 s-critical for fast firmware updates or logging in data acquisition systems. |
| DATA polling (I/O7) | Allows host CPU to poll completion without interrupts or timers; eliminates need for external status hardware. |
| Toggle bit (I/O6) | Removes requirement to store last written address/data for polling; simplifies software in multi-device EEPROM arrays. |
| JEDEC software data protection | Nonvolatile lock activated by 3-byte sequence; prevents accidental writes during power transitions without external circuitry. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data Retention |
|---|---|
|
Use Scenario: Storing I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during boot and runtime reconfiguration; 90 ns read speed ensures deterministic scan cycle timing. Use Value: Eliminates battery-backed SRAM; 100-year data retention guarantees parameter integrity across product lifetime without maintenance. |
Use Scenario: Holding factory-calibrated sensor offsets and gain coefficients in portable diagnostic equipment. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage for regulatory-required calibration records; software protection prevents unauthorized modification. Use Value: Meets IEC 62304 traceability requirements; 100,000 write cycles support field recalibration during service intervals. |
| Point-of-Sale Terminal Firmware Settings | Automated Test Equipment (ATE) Pattern Memory |
|
Use Scenario: Preserving tax rates, receipt formatting rules, and user preferences across power cycles in retail terminals. IC Role / Device Role / Timing Role: Byte-alterable EEPROM enabling selective update of individual settings without erasing full memory image. Use Value: Reduces firmware update latency; 5V-only operation simplifies power design versus Flash-based alternatives requiring charge pumps. |
Use Scenario: Storing test vectors and pass/fail thresholds in benchtop ATE systems where pattern changes occur daily. IC Role / Device Role / Timing Role: High-speed, reliable nonvolatile memory supporting rapid pattern reloads between test sequences. Use Value: 128-byte page write capability cuts pattern loading time by >90% compared to byte-by-byte writes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C256-15PU | 150 ns access time; PDIP-28 package; 100,000 endurance; no Toggle bit polling. | Slower timing limits use with >6.7 MHz bus clocks; through-hole only; lacks I/O6 status feedback. | Select when cost-sensitive, through-hole assembly required, and system timing budget allows ≥150 ns access. |
| M95256-DW DW | 5V SPI interface; SO8 package; 5 ms write cycle; 400 kHz clock; no parallel bus interface. | Requires serial peripheral interface instead of parallel address/data bus; incompatible pinout and protocol. | Select when board space is constrained and microcontroller has SPI peripherals; not a drop-in replacement. |
Compared with AT28C256-15PU and M95256-DW DW, the X28HC256JZ-90T1 delivers faster 90 ns parallel access, PLCC-32 surface-mount compatibility, and dual status-bit polling-making it optimal for legacy 5V microcontroller designs requiring deterministic, high-throughput EEPROM interaction.
Availability
X28HC256JZ-90T1 is available at Aetrix Electronics and suitable for industrial control systems, medical instrumentation, and point-of-sale terminals requiring stable component supply, long-lifecycle support, and RoHS-compliant manufacturing.
Supply support for X28HC256JZ-90T1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a provider of precision analog and power management ICs, serving industrial, infrastructure, and high-end consumer markets with high-reliability semiconductor solutions.
The X28HC256JZ-90T1 belongs to Intersil's second-generation CMOS EEPROM product line, designed specifically for robust, 5V-only nonvolatile storage in commercial-grade embedded systems where simplicity, reliability, and timing predictability are critical.
FAQ
What is the operating temperature range for the X28HC256JZ-90T1?
The X28HC256JZ-90T1 is specified for commercial operation from 0°C to +70°C. This range aligns with its "J" temperature grade designation and supports use in office equipment, test instruments, and consumer electronics where ambient conditions remain within this envelope. It is not rated for extended industrial (-40°C to +85°C) operation.
Does the X28HC256JZ-90T1 require external high-voltage programming circuitry?
No, the X28HC256JZ-90T1 operates with a single 5V supply and requires no external high-voltage programming circuitry. Its textured poly floating gate technology enables byte-alterable writes using only standard TTL/CMOS logic levels on CE, WE, and OE-eliminating charge pumps or VP-P generators.
How does the X28HC256JZ-90T1 indicate write completion to the host system?
The X28HC256JZ-90T1 provides two hardware-supported methods: DATA polling on I/O7 (returns complement of last written data until complete) and Toggle bit polling on I/O6 (toggles state on successive reads during programming). Both allow the host to detect completion without fixed delays or external interrupt lines.
What package type is used for the X28HC256JZ-90T1?
The X28HC256JZ-90T1 uses a 32-lead Plastic Leaded Chip Carrier (PLCC) package, RoHS-compliant, with dimensions conforming to JEDEC MS-016AE (N32.45x55). The "Z" suffix in the part number explicitly denotes RoHS compliance, and "T1" indicates tape-and-reel packaging.
Can the X28HC256JZ-90T1 be used as a direct replacement for older 28C256 devices?
The X28HC256JZ-90T1 is functionally and pin-compatible with industry-standard 28C256 EEPROMs but offers improved 90 ns access time, enhanced reliability via Direct Write™ cells, and integrated software data protection. Electrical and timing specifications meet or exceed legacy 28C256 requirements, enabling drop-in replacement in most 5V parallel bus designs.
X28HC256JZ-90T1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 256Kbit
- Memory Organization:
- 32K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
X28HC256JZ-90T1 FAQ
1.How can I place an order for X28HC256JZ-90T1 through Aetrix?
Please submit a Request for Quotation (RFQ) for X28HC256JZ-90T1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X28HC256JZ-90T1 reliable?
The price and inventory of X28HC256JZ-90T1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X28HC256JZ-90T1 is usually 5 days.
3.What payment methods are accepted for X28HC256JZ-90T1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X28HC256JZ-90T1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X28HC256JZ-90T1?
X28HC256JZ-90T1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X28HC256JZ-90T1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X28HC256JZ-90T1?
For technical support, including X28HC256JZ-90T1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X28HC256JZ-90T1 requirements.
6.How does Aetrix verify that X28HC256JZ-90T1 is sourced from the original manufacturer or authorized distributors?
All X28HC256JZ-90T1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X28HC256JZ-90T1 meets industry standards.
7.What is the process for return or replacement of X28HC256JZ-90T1?
All X28HC256JZ-90T1 units undergo pre-shipment inspection (PSI). If there is an issue with X28HC256JZ-90T1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X28HC256JZ-90T1 part is unused and in its original packaging.
Return procedure for X28HC256JZ-90T1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X28HC256JZ-90T1 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

