Renesas X28HC64D-90

Overview

X28HC64D-90 from Intersil is a 64 kbit (8k × 8) byte-alterable EEPROM operating from a single 5 V supply, featuring 90 ns access time, JEDEC-standard byte-wide pinout, and 64-byte page write capability enabling full memory rewrite in 0.25 s. It serves as nonvolatile configuration storage in industrial control modules requiring high endurance and long-term data retention.

For engineers reviewing the X28HC64D-90 datasheet, X28HC64D-90 pinout, X28HC64D-90 application, or X28HC64D-90 equivalent, key selection criteria include its 100,000 write cycles, 100-year data retention, software/hardware data protection modes, and compatibility with standard 8-bit memory buses in legacy embedded systems.

Technical Context

The X28HC64D-90 implements a floating-gate CMOS EEPROM array with dual-line control architecture (CE/OE/WE), supporting both CE- and WE-controlled write cycles. Its internal timing logic enables self-timed byte and page writes without external high-voltage circuitry or erase-before-write sequences.

End-of-write detection is implemented via two hardware-supported polling methods: DATA Polling on I/O7 (complement read during programming) and Toggle Bit polling on I/O6 (state toggling until completion). These features eliminate need for fixed delay loops or external interrupt signaling in host firmware.

Key Specifications

Pinout & Package

Package: 28-pin PDIP (Plastic Dual In-line Package), RoHS-compliant, 0.6-inch width, through-hole mounting. Pin 1 index corner marked with notch or dot per JEDEC MS-001.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar EEPROM applications.

Compared with AT28C64B-15PU and MX28LV640CT-90P, the X28HC64D-90 delivers optimal balance of speed, endurance, and single-supply simplicity for legacy 5 V embedded systems-no external VPP, no layout changes, and guaranteed 90 ns timing without derating.

Availability

X28HC64D-90 is available at Aetrix Electronics and suitable for industrial control, medical diagnostics, telecom infrastructure, and automotive body electronics requiring stable component supply across extended product lifecycles.

Supply support for X28HC64D-90 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil Corporation is a U.S.-based semiconductor company specializing in precision analog and power management ICs, acquired by Renesas Electronics in 2017.

The X28HC64 product line was designed for industrial and telecom applications demanding high-reliability, long-retention nonvolatile storage in 5 V systems with JEDEC-compatible footprints.

FAQ

What is the maximum operating temperature range for the X28HC64D-90?

The X28HC64D-90 is rated for commercial temperature operation from 0°C to +70°C. Its 28-pin PDIP package supports this range with thermal resistance θ_JA = 53°C/W. For extended temperature applications, the X28HC64PIZ-90 variant (-40°C to +85°C) is recommended. The X28HC64D-90 itself does not meet industrial temperature specifications.

Does the X28HC64D-90 require an external high-voltage supply for programming?

No, the X28HC64D-90 operates from a single 5 V supply with no external high-voltage (VPP) requirement. Internal charge pumps generate necessary programming voltages, eliminating need for 12 V rails or external circuitry. This distinguishes the X28HC64D-90 from older EPROMs and some competing EEPROMs like the MX28LV640CT-90P.

How does the software data protection feature work on the X28HC64D-90?

The X28HC64D-90 software data protection is enabled by writing three specific values (0xAA, 0x55, 0xA0) to addresses 0x5555, 0x2AAA, and 0x5555. Once set, all subsequent writes require repeating this sequence. The lock persists through power cycles and remains active until reset via a six-step deactivation command. The X28HC64D-90 ships unprotected by default.

Can the X28HC64D-90 be used as a direct replacement for SRAM in existing designs?

Yes, the X28HC64D-90 uses JEDEC-approved byte-wide pinout identical to standard 8k×8 SRAMs, enabling socket-level replacement. However, write operations require explicit CE/WE control and polling-unlike SRAM's transparent writes-so firmware must be updated to handle status checking via I/O6 or I/O7 before issuing next write.

What is the minimum pulse width required for WE and CE signals during write cycles on the X28HC64D-90?

The X28HC64D-90 requires minimum WE and CE pulse widths of 50 ns each, as specified in the AC Electrical Specifications table. This timing applies to both byte and page write operations. Violating this minimum may result in incomplete writes or data corruption. The X28HC64D-90's tWP and tCW parameters are strictly defined at 50 ns maximum, not typical.