Renesas X28HC64J-90
- Part No.:
- X28HC64J-90
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
X28HC64J-90.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:1,789
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Product details
Overview
X28HC64J-90 from Intersil is a 64 kbit (8k × 8), 5V-only, byte-alterable EEPROM in 32-lead PLCC package, featuring 90 ns access time, JEDEC-standard pinout, and hardware/software data protection. It supports page write (64-byte) with 2 ms typical byte write cycle and delivers 100,000 write endurance with >100-year data retention for industrial control configuration storage.
For engineers reviewing the X28HC64J-90 datasheet, X28HC64J-90 pinout, X28HC64J-90 application, or X28HC64J-90 equivalent, key selection criteria include its 90 ns read timing, 32-lead PLCC footprint, software data protection algorithm, page write capability, and compatibility with standard 8-bit memory bus architectures.
Technical Context
The X28HC64J-90 implements a two-line control architecture (CE/OE for reads, CE/WE for writes) to eliminate bus contention in multi-device memory arrays. Its internal floating-gate CMOS technology enables single 5V operation without external high-voltage programming circuits.
Write status detection is supported via DATA Polling (I/O7 complement behavior) and Toggle Bit (I/O6 toggling), both usable during active programming cycles. The device features default VCC-sense write inhibition below ~3V and configurable software data protection activated via a three-byte address sequence (0x1555, 0x0AAA, 0x1555).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 kbit (8,192 × 8-bit words) - provides sufficient nonvolatile storage for firmware parameters, calibration tables, or device configuration in embedded systems. |
| Access Time | 90 ns - ensures compatibility with legacy 8-bit microcontrollers and bus controllers operating at ≤11 MHz. |
| Write Cycle Time | 2 ms typical per byte - enables deterministic timing for host firmware without polling overhead when using fixed delays. |
| Page Write Capacity | 64 bytes - reduces total write time for sequential updates (e.g., logging or parameter blocks) to ~0.25 s for full memory rewrite. |
| Endurance / Retention | 100,000 write cycles / 100 years - meets long-life requirements for industrial equipment with infrequent but critical configuration changes. |
| Supply & Power | 5 V ±10%; 40 mA active max / 200 µA standby max - compatible with standard 5V logic rails and suitable for low-power standby modes. |
| Operating Range | 0°C to +70°C - rated for commercial temperature environments including office automation, point-of-sale terminals, and consumer electronics. |
Pinout & Package
Package: 32-lead Plastic Leaded Chip Carrier (PLCC), JEDEC MS-016AE, body size 12.5 mm × 12.5 mm, RoHS-compliant (Pb-free terminations).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | Select one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte page write operations. |
| I/O0–I/O7 | Data Input/Output | Bi-directional 8-bit data bus; I/O6 provides Toggle Bit status, I/O7 provides DATA Polling status during writes. |
| CE | Chip Enable | Primary device select; must be LOW for read/write; HIGH places outputs in high-impedance and reduces current to 200 µA. |
| OE | Output Enable | Controls output buffers; LOW enables data readout; used with CE for dual-line read control to prevent bus contention. |
| WE | Write Enable | Initiates write cycles; falling edge latches address/data; rising edge triggers internal programming; HIGH inhibits writes during power transitions. |
| VCC / VSS | Power / Ground | +5 V supply and return; requires local 0.1 µF ceramic decoupling per device plus 4.7 µF bulk capacitor per 8 devices. |
| NC | No Connect | Pins 3, 13, 29, 30 - unconnected internally; must remain unconnected on PCB to avoid reliability risk. |
Key Features
| Feature | Design Value |
|---|---|
| JEDEC-standard byte-wide pinout | Direct drop-in replacement for industry-standard SRAMs and EPROMs in existing 8-bit memory sockets and layouts. |
| Self-timed write with no erase-before-write | Eliminates pre-erase delays and complex erase sequencing-simplifies firmware and guarantees deterministic 2 ms write completion. |
| Hardware write protection | VCC-sense and CE/OE/WE control inhibit writes during power-up/down, preventing corruption without external circuitry. |
| Software data protection mode | Nonvolatile lock enabled via 3-byte command sequence; prevents accidental writes after initial configuration, enhancing field reliability. |
| DATA Polling and Toggle Bit | Two independent, bus-compatible status mechanisms allow flexible host-side write completion detection without interrupts or timers. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing I/O mapping, ladder logic parameters, and alarm thresholds in programmable logic controllers deployed in factory automation. IC Role / Device Role / Timing Role: Nonvolatile configuration memory accessed during boot and runtime via parallel 8-bit bus; 90 ns access supports real-time scan cycle timing. Use Value: Ensures deterministic startup and persistent settings across power cycles, with 100,000-cycle endurance matching expected maintenance intervals. | Use Scenario: Holding sensor calibration coefficients, user preferences, and safety-critical operational limits in portable diagnostic instruments. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store; software data protection prevents unintended overwrite during firmware updates or service mode. Use Value: Meets IEC 62304 Class B software requirements by guaranteeing data integrity over 100 years and supporting audit-ready write logging. |
| Point-of-Sale Terminal Settings | Telecom Line Card Identity Storage |
Use Scenario: Retaining tax rates, receipt formatting rules, and peripheral configuration in retail POS terminals operating in ambient commercial environments. IC Role / Device Role / Timing Role: Low-power, 5V-compatible EEPROM interfaced to 8-bit microcontroller; 200 µA standby current extends uptime during idle periods. Use Value: Enables zero-battery-backup design while preserving regulatory compliance data through frequent power cycling and firmware upgrades. | Use Scenario: Storing MAC addresses, firmware version stamps, and hardware revision IDs on telecom line cards in central office shelves. IC Role / Device Role / Timing Role: Parallel-configurable identity memory accessible during card initialization; JEDEC pinout ensures compatibility with legacy backplane bus protocols. Use Value: Supports hot-swap identification and inventory tracking without requiring rework of existing board layouts or driver stacks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| X28HC64JIZ-90 | Same 32-lead PLCC package, RoHS-compliant (matte tin finish), extended -40°C to +85°C temperature range. | Required for industrial-grade deployments where ambient temperature exceeds +70°C or Pb-free compliance is mandated. | Select X28HC64JIZ-90 when operating outside 0°C–70°C or for new designs requiring RoHS certification. |
| X28HC64PIZ-90 | 28-lead PDIP package, same -40°C to +85°C rating and RoHS compliance, but larger footprint and through-hole mounting. | Suitable for prototyping, repair, or legacy through-hole systems where PLCC socketing is unavailable or cost-prohibitive. | Choose X28HC64PIZ-90 only for hand-soldered prototypes, field replacements, or designs constrained to DIP footprints. |
Compared with X28HC64J-90, X28HC64JIZ-90 offers broader temperature tolerance and Pb-free termination for industrial use, while X28HC64PIZ-90 trades surface-mount compactness for through-hole serviceability-neither is pin-compatible, requiring layout change.
Availability
X28HC64J-90 is available at Aetrix Electronics and suitable for industrial PLC configuration storage, medical device calibration data retention, and point-of-sale terminal settings requiring stable component supply across extended product lifecycles.
Supply support for X28HC64J-90 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a provider of precision analog and power management ICs, acquired by Renesas Electronics in 2017; its legacy nonvolatile memory portfolio emphasizes reliability and industrial-grade specifications.
The X28HC64 product line was designed for byte-alterable, 5V-only EEPROM applications in embedded systems requiring JEDEC-compatible pinouts, deterministic write timing, and long-term data integrity without battery backup.
FAQ
What is the maximum operating temperature range for the X28HC64J-90?
The X28HC64J-90 is specified for commercial temperature operation from 0°C to +70°C. It is not rated for industrial (-40°C to +85°C) use; for that range, X28HC64JIZ-90 is the recommended alternative. Thermal resistance θJA is 41°C/W for the 32-lead PLCC package, and derating applies above +70°C.
Does the X28HC64J-90 require external high-voltage programming circuitry?
No, the X28HC64J-90 operates from a single 5V supply and requires no external high-voltage generators or VP-P control circuits. All programming is self-timed and internally managed, with write initiation controlled solely by CE and WE signals per JEDEC-standard timing.
How does software data protection work on the X28HC64J-90?
Software data protection on the X28HC64J-90 is enabled by writing three specific values (0xAA, 0x55, 0xA0) to addresses 0x1555, 0x0AAA, and 0x1555 respectively. Once set, the device remains write-protected until the six-step reset sequence is issued. The protection state is nonvolatile and persists across power cycles.
Can the X28HC64J-90 perform page writes, and what is the maximum page size?
Yes, the X28HC64J-90 supports page write operations up to 64 bytes. Consecutive writes must occur within 100 µs of each other and share the same A6–A12 page address. This allows full memory rewrite in ~0.25 seconds, significantly faster than individual byte writes.
Is the X28HC64J-90 pin-compatible with standard SRAMs or EPROMs?
Yes, the X28HC64J-90 uses the JEDEC-approved pinout for byte-wide memories and is designed to be compatible with industry-standard SRAMs and EPROMs. Its CE/OE/WE control scheme and 8-bit I/O bus allow direct substitution in existing 8-bit memory interfaces without logic redesign.
X28HC64J-90 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
X28HC64J-90 FAQ
1.How can I place an order for X28HC64J-90 through Aetrix?
Please submit a Request for Quotation (RFQ) for X28HC64J-90 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X28HC64J-90 reliable?
The price and inventory of X28HC64J-90 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X28HC64J-90 is usually 5 days.
3.What payment methods are accepted for X28HC64J-90?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X28HC64J-90 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X28HC64J-90?
X28HC64J-90 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X28HC64J-90 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X28HC64J-90?
For technical support, including X28HC64J-90 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X28HC64J-90 requirements.
6.How does Aetrix verify that X28HC64J-90 is sourced from the original manufacturer or authorized distributors?
All X28HC64J-90 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X28HC64J-90 meets industry standards.
7.What is the process for return or replacement of X28HC64J-90?
All X28HC64J-90 units undergo pre-shipment inspection (PSI). If there is an issue with X28HC64J-90, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X28HC64J-90 part is unused and in its original packaging.
Return procedure for X28HC64J-90:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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