Renesas X28HC64JIZ-90T1
- Part No.:
- X28HC64JIZ-90T1
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 32-LCC (J-Lead)
- Datasheet:
-
X28HC64JIZ-90T1.pdf
- Description:
- IC EEPROM 64KBIT PARALLEL 32PLCC
- Quantity:
- Payment:

- Shipping:

Inventory:2,717
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X28HC64JIZ-90T1 from Intersil is a 64 kbit (8k × 8) byte-alterable EEPROM operating from a single 5 V supply, featuring 90 ns read access time, JEDEC-standard byte-wide pinout, and 32-lead PLCC RoHS-compliant package. It supports page write (64-byte), DATA polling, and Toggle Bit polling for end-of-write detection, and is qualified for industrial temperature range (–40°C to +85°C) in embedded control and instrumentation systems.
For engineers reviewing the X28HC64JIZ-90T1 datasheet, X28HC64JIZ-90T1 pinout, X28HC64JIZ-90T1 application, or X28HC64JIZ-90T1 equivalent, key selection criteria include industrial-grade temperature rating, 90 ns access timing, software/hardware data protection modes, 100,000 write endurance, and compatibility with standard 5 V memory bus architectures.
Technical Context
The X28HC64JIZ-90T1 implements a floating-gate CMOS nonvolatile memory array with dual-line control (CE/OE/WE) enabling bus contention-free operation. Its architecture supports both CE- and WE-controlled write cycles, with address latching on the later falling edge and data latching on the earlier rising edge of CE or WE.
It integrates two real-time write status mechanisms-DATA Polling (I/O7 complement behavior) and Toggle Bit (I/O6 toggling)-and includes default VCC sense and write-inhibit logic for hardware-level data protection during power transitions. Software data protection is enabled via a nonvolatile 3-byte command sequence.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 64 kbit (8,192 × 8-bit words), sufficient for firmware storage, calibration tables, or configuration registers in microcontroller-based systems. |
| Access Time | 90 ns max - meets timing requirements for 11 MHz bus interfaces without wait states. |
| Write Cycle Time | 2 ms typical per byte or page - enables full memory rewrite in ~0.25 s, suitable for infrequent field updates. |
| Endurance | 100,000 write/erase cycles - supports long-term logging or parameter adjustment in industrial controllers. |
| Data Retention | 100 years at +25°C - ensures reliable storage of critical configuration data over product lifetime. |
| Supply Voltage | 5 V ±10% - operates directly from legacy 5 V logic rails without level-shifting or auxiliary regulators. |
| Temperature Range | –40°C to +85°C - certified for use in industrial automation, automotive body electronics, and outdoor equipment. |
| Package | 32-lead PLCC (RoHS-compliant, N32.45x55) - surface-mount compatible with wave-solder-reflow processes per IPC/JEDEC J-STD-020. |
Pinout & Package
32-lead Plastic Leaded Chip Carrier (PLCC), RoHS-compliant, JEDEC MS-016AE compliant, body size 12.5 mm × 12.5 mm × 3.5 mm (N32.45x55).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A12 | Address Inputs | 13-bit address bus selecting one of 8,192 memory locations; A6–A12 define page boundaries for 64-byte writes. |
| I/O0–I/O7 | Bi-directional Data Bus | 8-bit parallel interface for read/write; I/O6 = Toggle Bit, I/O7 = DATA Polling indicator during internal programming. |
| CE | Chip Enable | Primary device select; must be LOW for all operations; enables low-power standby when HIGH. |
| OE | Output Enable | Controls output buffers during reads; HIGH disables outputs to prevent bus contention. |
| WE | Write Enable | Initiates write cycles; falling edge latches address/data; rising edge triggers internal programming. |
| VCC | Power Supply | +5 V supply; supports 5 V-only operation with no external high-voltage programming circuitry. |
| VSS | Ground | Reference return path; decoupling capacitor (0.1 µF ceramic) required per device per datasheet. |
| NC | No Connect | Pins 3, 13, 29, 30 - unconnected internally; must remain unconnected on PCB. |
Key Features
| Feature | Design Value |
|---|---|
| Page Write (64-byte) | Reduces total programming time by >95% vs. byte-by-byte writes, enabling efficient bulk updates in system initialization or calibration routines. |
| DATA Polling (I/O7) | Eliminates fixed delay waits by allowing host CPU to poll completion status using simple bit-test loop, reducing software overhead. |
| Toggle Bit (I/O6) | Enables status checking without saving last address/data - ideal for multi-device arrays or multiprocessor environments. |
| Software Data Protection | Nonvolatile lock activated via 3-byte command sequence; prevents accidental writes during power-up/down without external hardware. |
| Hardware Write Inhibit | Automatic protection when VCC < 3 V, OE = LOW, WE = HIGH, or CE = HIGH - ensures data integrity across power transitions. |
| JEDEC Byte-Wide Pinout | Direct drop-in replacement for industry-standard SRAMs and EPROMs in existing 5 V memory designs, minimizing layout changes. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Data |
|---|---|
Use Scenario: Storing user-configurable I/O mapping, PID tuning parameters, and alarm thresholds in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration register bank accessed during boot and runtime via 5 V parallel bus. Use Value: 100,000-cycle endurance supports decades of field reconfiguration; 90 ns access enables real-time parameter recall without interrupt latency. | Use Scenario: Retaining factory-calibrated sensor offsets, gain coefficients, and safety-critical operational limits in diagnostic imaging equipment. IC Role / Device Role / Timing Role: Secure, tamper-resistant calibration memory with software/hardware write protection active during power cycling. Use Value: 100-year data retention guarantees accuracy over device lifetime; Toggle Bit polling simplifies multi-sensor synchronization in embedded firmware. |
| Automotive Body Control Module | Test & Measurement Equipment Setup |
Use Scenario: Saving seat/mirror position presets, lighting profiles, and door lock configurations in 12 V vehicle systems with 5 V logic rails. IC Role / Device Role / Timing Role: Industrial-temp EEPROM interfaced to MCU via shared memory bus; withstands under-hood thermal cycling. Use Value: –40°C to +85°C qualification ensures reliability across environmental extremes; page write accelerates personalization setup during vehicle startup. | Use Scenario: Storing instrument-specific test sequences, probe compensation values, and user-defined measurement ranges in benchtop analyzers. IC Role / Device Role / Timing Role: Field-updatable configuration store accessed during self-test and calibration routines. Use Value: DATA polling reduces firmware wait time during automated calibration; RoHS-compliant PLCC supports lead-free manufacturing compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT28C64B-15PU | 150 ns access time, 28-pin PDIP only, no RoHS option in original packaging, 10,000-cycle endurance. | Limited to commercial temp (0°C to +70°C); lacks page write and Toggle Bit polling. | Select only for legacy through-hole designs where 90 ns timing and industrial temp are not required. |
| M95640-DW | Serial SPI interface, 5 MHz max clock, 5 ms write cycle, SO8 package, 400 kHz I²C-compatible variant available. | Requires serial protocol stack; incompatible pinout and bus architecture; lower power but slower effective throughput. | Choose for space-constrained designs needing serial interface or ultra-low standby current (<5 µA), not parallel bus replacement. |
Compared with AT28C64B-15PU and M95640-DW, the X28HC64JIZ-90T1 delivers faster parallel access, industrial temperature support, and advanced write-status feedback - making it optimal for real-time embedded systems requiring deterministic 5 V memory performance and long-term data integrity.
Availability
X28HC64JIZ-90T1 is available at Aetrix Electronics and suitable for industrial PLCs, medical calibration systems, automotive body controllers, and test equipment requiring stable component supply with guaranteed RoHS compliance and extended lifecycle support.
Supply support for X28HC64JIZ-90T1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a pioneer in precision analog and power management ICs, now part of Renesas Electronics, delivering high-reliability solutions for industrial, infrastructure, and automotive markets.
The X28HC64 product line was designed for robust, 5 V-compatible nonvolatile memory applications demanding byte-alterability, industrial temperature operation, and hardware/software dual-protection - targeting embedded systems where firmware resilience and field configurability are critical.
FAQ
What is the maximum operating temperature range for the X28HC64JIZ-90T1?
The X28HC64JIZ-90T1 is rated for industrial temperature operation from –40°C to +85°C, verified per Intersil's characterization and documented in the FN8109 Rev 4.00 datasheet. This range ensures reliable functionality in harsh environments such as factory automation controllers and automotive under-hood modules. The X28HC64JIZ-90T1 maintains full electrical specifications-including 90 ns access time and 2 ms write cycle-across this entire range.
Does the X28HC64JIZ-90T1 require external high-voltage programming circuitry?
No, the X28HC64JIZ-90T1 operates from a single 5 V supply with no external high-voltage circuitry required. Its internal charge pump handles all programming voltages, enabling direct connection to standard 5 V logic buses. This eliminates the need for VP-P generators or complex programming algorithms-confirmed in the "Simple byte and page write" feature list and "Single 5V supply" specification of the X28HC64JIZ-90T1 datasheet.
How does the software data protection feature work on the X28HC64JIZ-90T1?
The X28HC64JIZ-90T1 software data protection is enabled via a nonvolatile 3-byte command sequence written to specific addresses (0x5555, 0x2AAA, 0x5555). Once set, it remains active for the device's lifetime unless reset by a 6-step deactivation algorithm. This feature prevents accidental writes during power transitions and runtime, and is distinct from hardware protection (VCC sense, CE/OE/WE inhibit). The X28HC64JIZ-90T1 ships unprotected by default.
Can the X28HC64JIZ-90T1 be used as a direct replacement for standard SRAMs in existing designs?
Yes-the X28HC64JIZ-90T1 uses the JEDEC-approved pinout for byte-wide memories and is electrically compatible with industry-standard 5 V SRAMs in read mode. Its dual-line control (CE/OE) eliminates bus contention, and its 90 ns access time matches common SRAM timing. However, write cycles require explicit WE strobing and status polling; unlike SRAM, it is not write-transparent. The X28HC64JIZ-90T1 serves as a functional drop-in for read-dominant applications with infrequent nonvolatile updates.
What is the purpose of the Toggle Bit (I/O6) and DATA Polling (I/O7) functions in the X28HC64JIZ-90T1?
The Toggle Bit (I/O6) toggles state on successive reads during internal programming and stops when complete; DATA Polling (I/O7) returns the complement of the last written byte until programming finishes. Both provide real-time, hardware-assisted write completion detection-eliminating fixed delays and enabling optimized firmware loops. These features are fully implemented in the X28HC64JIZ-90T1 and documented in Figures 2, 5, and 19 of the FN8109 datasheet.
X28HC64JIZ-90T1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 32-LCC (J-Lead)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 64Kbit
- Memory Organization:
- 8K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-PLCC (13.97x11.43)
X28HC64JIZ-90T1 FAQ
1.How can I place an order for X28HC64JIZ-90T1 through Aetrix?
Please submit a Request for Quotation (RFQ) for X28HC64JIZ-90T1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X28HC64JIZ-90T1 reliable?
The price and inventory of X28HC64JIZ-90T1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X28HC64JIZ-90T1 is usually 5 days.
3.What payment methods are accepted for X28HC64JIZ-90T1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X28HC64JIZ-90T1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X28HC64JIZ-90T1?
X28HC64JIZ-90T1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X28HC64JIZ-90T1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X28HC64JIZ-90T1?
For technical support, including X28HC64JIZ-90T1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X28HC64JIZ-90T1 requirements.
6.How does Aetrix verify that X28HC64JIZ-90T1 is sourced from the original manufacturer or authorized distributors?
All X28HC64JIZ-90T1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X28HC64JIZ-90T1 meets industry standards.
7.What is the process for return or replacement of X28HC64JIZ-90T1?
All X28HC64JIZ-90T1 units undergo pre-shipment inspection (PSI). If there is an issue with X28HC64JIZ-90T1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X28HC64JIZ-90T1 part is unused and in its original packaging.
Return procedure for X28HC64JIZ-90T1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X28HC64JIZ-90T1 Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

