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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Supervisors

Renesas X40035V14-C

Name: X40035V14-C
Brand: Renesas
SKU: X40035V14-C
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: X40035V14-C

Manufacturer:: Renesas

Category:: Supervisors

Package:: 14-TSSOP (0.173", 4.40mm Width)

Datasheet:: X40035V14-C.pdf

Description:: IC SUPERVISOR 3 CHANNEL 14TSSOP

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Product details

Overview

X40035V14-C from Xicor (now Renesas) is a triple-voltage supervisor IC with integrated CPU reset controller, watchdog timer, and I²C interface. It monitors V_CC (V1), V2MON, and V3MON at factory-programmed thresholds (4.55–4.65 V, 1.25–1.35 V, 2.85–2.95 V), asserts active-HIGH RESET on V_CC brownout, provides debounced manual reset, and supports 25 ms / 200 ms / 1.4 s watchdog intervals - used in network storage controllers for reliable power sequencing and fault recovery.

For engineers reviewing the X40035V14-C datasheet, X40035V14-C pinout, X40035V14-C application, or X40035V14-C equivalent, key selection criteria include its triple independent voltage monitoring capability, programmable reset timeout (50/200/400/800 ms), 400 kHz I²C configuration interface, low 6 µA standby current (watchdog off), and 14-pin SOIC/TSSOP package compatibility with industrial-grade supply supervision requirements.

Technical Context

The X40035V14-C implements three independent voltage comparators - one referenced to V_CC (V1MON), one powered by V_CC but sensing V2MON, and one fully independent (V3MON supplied directly) - enabling simultaneous monitoring of regulated and unregulated rails. Its reset logic combines power-on delay, low-V_CC detection, and manual reset with glitch immunity.

Watchdog functionality relies on SDA/SCL activity detection using a dedicated state machine; timeout intervals are set via nonvolatile WD1/WD0 bits (25 ms, 200 ms, 1.4 s, or disabled). The I²C interface operates at 400 kHz with slave address 0xA0h, supports register-level access to control, fault detection, and programmable trip points, and includes write protection via WP pin and volatile WEL/RWEL latches.

Key Specifications

Parameter	Value and Actual Design Meaning
V_TRIP1	4.55–4.65 V: Factory-set V_CC reset threshold ensures stable 5 V system startup before processor execution.
V_TRIP2	1.25–1.35 V: Fixed threshold for V2MON input, suitable for monitoring 1.5 V auxiliary rails without external dividers.
V_TRIP3	2.85–2.95 V: Fixed threshold for V3MON input, optimized for 3.3 V or 3 V supply fail detection.
t_PURST	200 ms (factory default): Power-up reset pulse duration prevents premature MCU initialization during rail stabilization.
Watchdog interval	25 ms / 200 ms / 1.4 s / off: Selectable via nonvolatile control bits; enables precise firmware hang detection timing.
Standby current	6 µA typical (watchdog off): Enables ultra-low-power supervision in always-on subsystems.
I²C speed	400 kHz: Supports fast configuration and status reads without requiring slow bus arbitration.
Supply range	2.7 V to 5.5 V: Covers standard 3.3 V and 5 V logic domains while maintaining full supervision functionality.

Pinout & Package

Package: 14-lead SOIC or TSSOP (JEDEC MS-012 / MO-153 compliant); body dimensions 8.65 mm × 3.90 mm × 1.75 mm; lead pitch 1.27 mm; RoHS-compliant matte tin lead finish.

Pin/Terminal	Circuit Role	Design Meaning
1 V2FAIL	Open-drain V2MON fault indicator	Asserts LOW when V2MON < V_TRIP2; requires external pull-up; no power-up delay - enables immediate power-fail interrupt signaling.
2 V2MON	V2 voltage monitor input	Senses second supply rail; comparator powered by V_CC - must be biased within 0.9–3.5 V range for valid operation.
3 LOWLINE	Early V_CC undervoltage flag	CMOS output that goes LOW before RESET assertion - provides advance warning for graceful shutdown sequences.
4 NC	No-connect	Not internally bonded; must remain unconnected per datasheet to avoid parasitic coupling or latch-up risk.
5 MR	Debounced manual reset input	Active-LOW pushbutton interface; internal RC filter eliminates bounce; holds RESET for t_PURST after release.
6 RESET	Active-HIGH reset output	CMOS output asserted HIGH during V_CC brownout or MR activation - directly drives reset inputs of 3.3 V/5 V MCUs.
7 V_SS	Ground reference	Primary return path for all internal analog comparators and digital logic; must be low-impedance connection to system ground plane.
8 SDA	I²C bidirectional data line	Open-drain interface with always-active input buffer; requires external 2.2–10 kΩ pull-up; supports read/write to control/fault registers.
9 SCL	I²C clock input	Controls serial timing; master-generated edge-triggered clock; tolerates 400 kHz max frequency with standard-mode timing.
10 WP	Hardware write protect	Logic HIGH disables all register writes including V_TRIP programming - prevents accidental corruption during system operation.
11 V3MON	V3 voltage monitor input	Senses third supply rail; comparator powered directly by V3MON - supports true independence from V_CC failure.
12 V3FAIL	Open-drain V3MON fault indicator	Asserts LOW when V3MON < V_TRIP3; no power-up delay - enables real-time notification of third-rail collapse.
13 WDO	Watchdog timeout output	Open-drain active-LOW signal indicating MCU hang; can be wired OR with other fault signals or drive external reset logic.
14 V_CC	Main supply input	Power source for digital core and V1/V2 comparators; supplies internal bias circuits; valid from 2.7 V to 5.5 V.

Key Features

Feature	Design Value
Triple independent voltage monitoring	Simultaneous supervision of V_CC, V2MON (V_CC-powered), and V3MON (self-powered) enables full-system power integrity verification without external components.
Programmable reset timeout	Four selectable t_PURST values (50/200/400/800 ms) allow matching of reset hold time to specific processor boot requirements and oscillator stabilization delays.
Configurable watchdog timer	Nonvolatile WD1/WD0 bits retain selected timeout across power cycles - eliminates need for firmware reinitialization after each reboot.
Early low-V_CC detection (LOWLINE)	Dedicated CMOS output triggers before RESET assertion - provides 10–100 µs advance notice for controlled data save or state preservation.
Fault detection register (FDR)	Volatile 8-bit register (address 0xFF) captures root cause of last reset (LV1F/LV2F/LV3F/WDF/MRF) - simplifies field failure analysis and diagnostics.
V_TRIP threshold adjustability	Factory-default thresholds can be reprogrammed via high-voltage sequence on WDO pin - supports fine-tuning for ±1% tolerance applications.

Applications

Network Storage Controllers	Rack-Mounted Servers
Use Scenario: Monitoring 5 V main, 3.3 V I/O, and 1.5 V memory rails in RAID controller boards where simultaneous power loss on any rail must trigger safe shutdown. IC Role / Device Role / Timing Role: Triple-voltage supervisor asserting RESET and generating early LOWLINE warning to initiate cache flush and controller halt before data corruption occurs. Use Value: Prevents filesystem corruption and hardware lockup by ensuring coordinated reset across all voltage domains with sub-millisecond response to rail collapse.	Use Scenario: Supervising redundant 5 V and 3.3 V power supplies in dual-CPU server motherboards with hot-swap capability. IC Role / Device Role / Timing Role: Independent V2MON/V3MON inputs track secondary supplies; V2FAIL/V3FAIL outputs feed into FPGA-based power management logic for dynamic rail disable. Use Value: Enables automatic failover between primary and backup PSUs without host intervention, improving system uptime and reducing MTTR.
Industrial PLC Backplanes	Telecom Line Cards
Use Scenario: Ensuring deterministic startup and brownout recovery in modular PLC chassis with mixed 24 V DC input, 5 V logic, and 3.3 V FPGA rails. IC Role / Device Role / Timing Role: Power-on reset generator with 200 ms t_PURST and debounced MR input synchronizes firmware load across distributed I/O modules. Use Value: Eliminates race conditions during cold start and guarantees consistent module enumeration order across temperature ranges (−40°C to +85°C).	Use Scenario: Monitoring 5 V, 3.3 V, and 1.2 V DSP core supplies in carrier-grade Ethernet line cards subject to transient surges and thermal cycling. IC Role / Device Role / Timing Role: Watchdog timer with 25 ms interval detects DSP firmware hangs caused by packet buffer overruns or PHY lockups. Use Value: Restores link connectivity within 50 ms of hang detection - meets ITU-T G.8261 jitter tolerance and service-level agreement (SLA) requirements.

Network Storage Controllers

Rack-Mounted Servers

Use Scenario: Monitoring 5 V main, 3.3 V I/O, and 1.5 V memory rails in RAID controller boards where simultaneous power loss on any rail must trigger safe shutdown.

IC Role / Device Role / Timing Role: Triple-voltage supervisor asserting RESET and generating early LOWLINE warning to initiate cache flush and controller halt before data corruption occurs.

Use Value: Prevents filesystem corruption and hardware lockup by ensuring coordinated reset across all voltage domains with sub-millisecond response to rail collapse.

Use Scenario: Supervising redundant 5 V and 3.3 V power supplies in dual-CPU server motherboards with hot-swap capability.

IC Role / Device Role / Timing Role: Independent V2MON/V3MON inputs track secondary supplies; V2FAIL/V3FAIL outputs feed into FPGA-based power management logic for dynamic rail disable.

Use Value: Enables automatic failover between primary and backup PSUs without host intervention, improving system uptime and reducing MTTR.

Industrial PLC Backplanes

Telecom Line Cards

Use Scenario: Ensuring deterministic startup and brownout recovery in modular PLC chassis with mixed 24 V DC input, 5 V logic, and 3.3 V FPGA rails.

IC Role / Device Role / Timing Role: Power-on reset generator with 200 ms t_PURST and debounced MR input synchronizes firmware load across distributed I/O modules.

Use Value: Eliminates race conditions during cold start and guarantees consistent module enumeration order across temperature ranges (−40°C to +85°C).

Use Scenario: Monitoring 5 V, 3.3 V, and 1.2 V DSP core supplies in carrier-grade Ethernet line cards subject to transient surges and thermal cycling.

IC Role / Device Role / Timing Role: Watchdog timer with 25 ms interval detects DSP firmware hangs caused by packet buffer overruns or PHY lockups.

Use Value: Restores link connectivity within 50 ms of hang detection - meets ITU-T G.8261 jitter tolerance and service-level agreement (SLA) requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar triple-voltage supervisor applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX6816ESE+	Single-supply supervisor (V_CC only); no V2MON/V3MON inputs; fixed 200 ms reset timeout; no I²C interface.	Limited to basic 5 V or 3.3 V systems without multi-rail monitoring needs.	Select when only V_CC supervision is required and board space is constrained - lacks triple-monitoring capability of X40035V14-C.
TPS3808G33DBVR	Dual-voltage supervisor (V_CC + V_SENSE); fixed 3.08 V / 3.3 V thresholds; no programmable trip points; no fault register.	Suitable for cost-sensitive dual-rail applications but cannot replace full triple-monitoring function.	Choose for simpler 2-rail designs where V3MON independence and I²C configurability are not needed - lower BOM cost than X40035V14-C.

Compared with MAX6816ESE+ and TPS3808G33DBVR, the X40035V14-C uniquely delivers three independent voltage monitoring channels, I²C-based configuration of reset timing and watchdog intervals, and a fault detection register - making it the only option among the three capable of full-system power integrity management in complex multi-supply embedded platforms.

Availability

X40035V14-C is available at Aetrix Electronics and suitable for network storage, rack-mounted servers, and industrial PLC backplanes requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for X40035V14-C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xicor Inc., acquired by Renesas Electronics in 2008, specialized in nonvolatile memory and power management ICs with focus on high-reliability industrial and telecom applications.

The X4003x family was designed specifically for embedded systems requiring coordinated multi-rail power supervision, watchdog protection, and I²C-based configuration - targeting communication infrastructure and industrial control markets.

FAQ

What is the factory-default reset timeout setting for the X40035V14-C?

The X40035V14-C ships with t_PURST set to 200 ms, configured via nonvolatile PUP1/PUP0 bits (01 binary). This value ensures sufficient time for 5 V and 3.3 V supply stabilization and crystal oscillator startup before releasing the active-HIGH RESET signal. The timeout can be reprogrammed to 50 ms, 400 ms, or 800 ms using the I²C interface and Control Register write sequence.

Does the X40035V14-C support independent monitoring of an unregulated supply?

Yes - the V3MON input on the X40035V14-C is powered directly by the sensed voltage, enabling true independence from V_CC. When V3MON drops below its 2.85–2.95 V threshold, the open-drain V3FAIL output asserts LOW even if V_CC has failed completely. This allows monitoring of unregulated rails such as +12 V or +5 V standby supplies without external regulators or level shifters.

How does the watchdog timer on the X40035V14-C get reset?

The X40035V14-C watchdog timer is reset by a specific I²C sequence: a START condition, followed by toggling SCL from HIGH to LOW while SDA remains HIGH, then issuing a STOP condition. This "WDT restart" command must occur within the selected timeout interval (25 ms / 200 ms / 1.4 s). Unlike standard I²C reads/writes, no slave address or data bytes are required - only the defined clock/data edge transitions.

Can the voltage thresholds of the X40035V14-C be modified after soldering?

Yes - the V_TRIP1, V_TRIP2, and V_TRIP3 thresholds of the X40035V14-C can be reprogrammed in-circuit using a high-voltage programming sequence applied to the WDO pin. This requires applying the target threshold voltage to the corresponding monitor input (V_CC, V2MON, or V3MON), pulsing WDO to V_PP (~12 V), and executing an I²C write to the appropriate address (01h/09h/0Dh). The procedure is detailed in the datasheet section "VTRIPX Set/Reset Conditions".

What is the purpose of the LOWLINE pin on the X40035V14-C?

The LOWLINE pin on the X40035V14-C is a CMOS output that goes LOW earlier than the RESET signal when V_CC falls below V_TRIP1. Unlike RESET, it has no power-up delay circuitry - providing immediate notification of incipient brownout. This allows host processors or FPGAs to execute emergency actions (e.g., cache flush, state save) before the system reset is asserted, improving data integrity in mission-critical applications.

X40035V14-C Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 14-TSSOP (0.173", 4.40mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Multi-Voltage Supervisor

Number of Voltages Monitored:: 3

Voltage - Threshold:: 1V, 2.9V, 4.6V

Output:: Open Drain or Open Collector

Reset:: Active Low

Reset Timeout:: Adjustable/Selectable

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 14-TSSOP

X40035V14-C FAQ

1.How can I place an order for X40035V14-C through Aetrix?

Please submit a Request for Quotation (RFQ) for X40035V14-C on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for X40035V14-C reliable?

The price and inventory of X40035V14-C are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X40035V14-C is usually 5 days.

3.What payment methods are accepted for X40035V14-C?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X40035V14-C transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for X40035V14-C?

X40035V14-C orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your X40035V14-C order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for X40035V14-C?

For technical support, including X40035V14-C datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X40035V14-C requirements.

6.How does Aetrix verify that X40035V14-C is sourced from the original manufacturer or authorized distributors?

All X40035V14-C products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X40035V14-C meets industry standards.

7.What is the process for return or replacement of X40035V14-C?

All X40035V14-C units undergo pre-shipment inspection (PSI). If there is an issue with X40035V14-C, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The X40035V14-C part is unused and in its original packaging.

Return procedure for X40035V14-C:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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