Renesas X40420S14I-B
- Part No.:
- X40420S14I-B
- Manufacturer:
- Renesas
- Category:
- Supervisors
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
X40420S14I-B.pdf
- Description:
- IC SUPERVISOR 2 CHANNEL 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:413
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X40420S14I-B from Xicor (now part of Renesas) is a dual-voltage supervisor IC with integrated 4kbit EEPROM, watchdog timer, manual reset input, and battery-switched VOUT. It provides power-on reset (tPURST = 200ms default), dual threshold monitoring (VTRIP1 = 4.6V ±1%, VTRIP2 = 2.6V ±2%), and 5mA–50mA system backup switching - used in industrial controllers and network servers for brownout protection and SRAM retention.
For engineers reviewing the X40420S14I-B datasheet, X40420S14I-B pinout, X40420S14I-B application, or X40420S14I-B equivalent, key selection criteria include its dual-supply fail detection logic, programmable VTRIP2 down to 0.9V, 400kHz I²C interface, 25µA standby current (watchdog on), and 14-pin SOIC/TSSOP package compatibility.
Technical Context
The X40420S14I-B implements two independent voltage comparators: one monitors VCC against fixed 4.6V VTRIP1, the other monitors V2MON against factory-set 2.6V VTRIP2 (reprogrammable to 0.9V). Its reset output is active-HIGH open-drain (X40420 variant), asserted during VCC < VTRIP1 or MR assertion, with tPURST configurable to 50/200/400/800ms.
It integrates a watchdog timer triggered by I²C activity (SDA/SCL transitions), with timeout options of 25ms/200ms/1.4s or disabled; a battery switch that routes VOUT to VBATT when VCC drops below VTRIP1 and VBATT – 0.03V; and 4kbit Block Lock™ EEPROM organized as 512 × 8, accessible via 2-wire interface at up to 400kHz.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VTRIP1 | 4.6V ±1% - primary supply monitor threshold; asserts RESET when VCC falls below this level. |
| VTRIP2 | 2.6V ±2% - secondary monitor threshold (suffix -B); programmable down to 0.9V for custom power-fail warning. |
| tPURST | 200ms default - power-on reset timeout; selectable via nonvolatile control bits (50/200/400/800ms). |
| Watchdog timeout | 200ms default - factory-disabled; enabled via WD1/WD0 bits; restarts on valid I²C START/STOP sequence. |
| EEPROM capacity | 4kbit (512 × 8) - supports 16-byte page writes; 5ms typical write cycle; 100,000 endurance cycles. |
| VOUT drive capability | 50mA from VCC, 250µA from VBATT - powers external SRAM during main supply failure with hysteresis-controlled switchover. |
| Supply range | 2.7V to 5.5V - operates across standard 3.3V and 5V logic rails; RESET remains valid down to VCC = 1V. |
Pinout & Package
Package: 14-lead SOIC (Small Outline Integrated Circuit) and TSSOP (Thin Shrink Small Outline Package), both RoHS-compliant, 1.27mm pitch, body width 3.9mm (SOIC) / 4.4mm (TSSOP).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 V2FAIL | Open-drain fail indicator | Active-LOW signal indicating V2MON < VTRIP2; no power-up delay; requires external pull-up. |
| 2 V2MON | Secondary voltage monitor input | Accepts unregulated or second supply; threshold set to 2.6V (X40420S14I-B); programmable via I²C sequence. |
| 3 LOWLINE | Early low-VCC detect output | Open-drain active-LOW signal when VCC < VTRIP1; used for preemptive brownout warning. |
| 4 WDO | Watchdog timeout output | Active-LOW open-drain output; asserts when watchdog timer expires; used to trigger system recovery. |
| 5 MR | Manual reset input | Debounced active-LOW input; internal pull-up; initiates reset pulse lasting tPURST. |
| 6 RESET | Active-HIGH reset output (X40420) | Open-drain active-HIGH output; asserted during VCC undervoltage or MR event; holds for tPURST. |
| 7 VSS | Ground reference | Primary ground connection; must be connected to system common ground plane. |
| 8 SDA | I²C bidirectional data line | Open-drain serial data; supports 400kHz operation; used for EEPROM access and configuration register reads/writes. |
| 9 SCL | I²C clock input | Input-only clock line; controls timing of all serial transfers; requires external pull-up. |
| 10 WP | Write protect enable | Active-HIGH input; disables all writes (EEPROM and registers) when pulled HIGH; internal pull-down (~10MΩ). |
| 11 VBATT | Battery backup supply input | Provides backup power source; connects to VOUT when VCC fails; connect to ground if unused. |
| 12 VOUT | System backup output | Switched output sourcing 50mA from VCC or 250µA from VBATT; powers SRAM during power loss. |
| 13 BATT-ON | Battery active status indicator | CMOS output HIGH when VOUT is sourced from VBATT; drives external PNP transistor for higher-current operation. |
| 14 VCC | Main supply input | Primary power rail (2.7–5.5V); powers all internal circuits except EEPROM during write cycles. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent voltage supervision | Simultaneous monitoring of VCC and V2MON enables early power-fail detection and redundant system safety checks. |
| Programmable VTRIP2 threshold | Adjustable from factory 2.6V down to 0.9V using I²C command sequence - eliminates need for external resistor dividers in precision applications. |
| Integrated battery-switched VOUT | Automatically switches to VBATT with 60mV hysteresis when VCC drops below VTRIP1 and VBATT – 0.03V - ensures clean SRAM retention without external MOSFETs. |
| Nonvolatile control register | Stores tPURST, watchdog timeout, and block-lock settings across power cycles - enables field-configurable behavior without firmware changes. |
| Block Lock™ EEPROM protection | Hardware-enforced write protection for upper 256 bytes (BP = 1) or full array (BP = 0) - prevents accidental corruption of critical configuration data. |
| Low-power standby operation | 6µA typical current with watchdog disabled - suitable for battery-backed systems requiring multi-year shelf life. |
Applications
| Industrial Process Controller | Network Router Power Management |
|---|---|
|
Use Scenario: PLCs and distributed I/O modules operating in harsh environments with fluctuating 24V DC supplies converted to 5V/3.3V rails. IC Role / Device Role / Timing Role: Dual-voltage supervisor monitors both regulated 5V logic rail and auxiliary 3.3V I/O rail; asserts RESET on either undervoltage to halt CPU execution before data corruption. Use Value: Prevents spurious state transitions during brownouts; preserves SRAM contents via VOUT/VBATT switchover; eliminates need for discrete supervisors and backup diodes. |
Use Scenario: Carrier-grade routers with hot-swappable line cards requiring deterministic power sequencing and fail-safe memory retention. IC Role / Device Role / Timing Role: Monitors primary 5V supply (VTRIP1) and unregulated 12V intermediate bus (V2MON via resistor divider); triggers V2FAIL interrupt for predictive power-fail handling. Use Value: Enables graceful shutdown of packet buffers; maintains MAC address tables in SRAM during brief AC outages; reduces MTTR via fault detection register logging. |
| Desktop Motherboard BIOS Protection | Medical Diagnostic Equipment |
|
Use Scenario: ATX motherboards where CMOS real-time clock and BIOS configuration must survive AC power loss. IC Role / Device Role / Timing Role: Provides power-on reset with 200ms tPURST, monitors +5VSB standby rail, and backs up RTC SRAM via VBATT input from coin cell. Use Value: Guarantees reliable boot initialization after cold start; prevents BIOS corruption during sudden power loss; simplifies layout with single-chip solution. |
Use Scenario: Portable ultrasound devices with lithium battery backup and strict IEC 60601-1 power integrity requirements. IC Role / Device Role / Timing Role: Supervises main 3.3V system rail and battery voltage; uses watchdog to detect firmware hangs; stores calibration data in protected EEPROM. Use Value: Ensures patient data persistence during battery swaps; meets Class BF isolation requirements via galvanically isolated reset signaling; supports audit-trail logging in nonvolatile memory. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-supply supervisor with EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6820ETA+ | Single-supply monitor (VCC only); no V2MON input; 256-byte EEPROM; 10-pin µMAX package. | Lacks secondary voltage monitoring and battery switchover; suitable only for basic reset + memory needs. | Select when dual-monitoring is unnecessary and board space is constrained; verify tPURST and EEPROM size match requirements. |
| TPS3823MPW | Dual-supply monitor (4.63V/2.93V thresholds); no EEPROM; no battery switch; 8-pin SOIC; 3.5µA quiescent current. | Requires external EEPROM and discrete battery switch circuit; lower power but higher BOM count. | Choose when ultra-low standby current is critical and system design allows separation of supervision and memory functions. |
Compared with MAX6820ETA+ and TPS3823MPW, the X40420S14I-B uniquely integrates dual-voltage supervision, battery-backed VOUT, and 4kbit EEPROM in a single 14-pin package - reducing component count, PCB area, and qualification effort for systems requiring coordinated power fail response and nonvolatile storage.
Availability
X40420S14I-B is available at Aetrix Electronics and suitable for industrial process controllers, network routers, desktop motherboards, and medical diagnostic equipment requiring stable component supply, long-lifecycle support, and guaranteed traceability.
Supply support for X40420S14I-B includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Xicor was a fabless semiconductor company specializing in nonvolatile memory and power management ICs, acquired by Renesas Electronics in 2008. Its legacy products emphasize reliability, low power, and integration for embedded systems.
The X40420/X40421 family was designed to consolidate power-on reset, watchdog, dual-supply monitoring, battery backup switching, and EEPROM into one die - targeting cost-sensitive, space-constrained applications in communications and industrial automation.
FAQ
What is the reset polarity of the X40420S14I-B?
The X40420S14I-B features an active-HIGH open-drain RESET output (pin 6), consistent with the X40420 variant designation. This differs from the X40421's active-LOW RESET. The output remains HIGH during normal operation and goes LOW only during power-up, brownout, or manual reset events - ensuring compatibility with microcontrollers expecting high-active reset signaling.
Can the VTRIP2 threshold of the X40420S14I-B be reprogrammed?
Yes, the X40420S14I-B's VTRIP2 threshold (factory-set to 2.6V ±2%) can be reprogrammed down to 0.9V using a defined I²C sequence involving WDO pin voltage control and specific slave address writes (A0h, byte address 09h). This procedure requires VCC = 5V and does not affect EEPROM contents - enabling precise tailoring for custom power-fail warning levels.
How does the battery switchover function work in the X40420S14I-B?
The X40420S14I-B's battery switchover activates when VCC drops below VTRIP1 (4.6V) and VBATT – 0.03V. VOUT then connects to VBATT through an 80Ω switch, supplying up to 250µA to preserve SRAM data. Hysteresis (±0.03V) prevents oscillation near the threshold. BATT-ON (pin 13) goes HIGH to indicate battery mode - allowing external circuit control.
What is the maximum I²C clock frequency supported by the X40420S14I-B?
The X40420S14I-B supports standard-mode I²C operation up to 400kHz, as specified in its datasheet. This allows efficient access to its 4kbit EEPROM and configuration registers without requiring slow bit-banged interfaces. The SDA and SCL pins include internal input buffers and open-drain outputs, requiring external pull-up resistors per I²C bus specifications.
Does the X40420S14I-B include hardware write protection for its EEPROM?
Yes, the X40420S14I-B implements Block Lock™ hardware write protection controlled by the BP bit in its nonvolatile control register. When BP = 1, writes to addresses 0x100–0x1FF (upper 256 bytes) are blocked; when BP = 0, the entire EEPROM array is unprotected. Additional protection is provided by the WP pin (pin 10), which globally disables all writes when driven HIGH.
X40420S14I-B Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 2
- Voltage - Threshold:
- 2.6V, 4.6V
- Output:
- Open Drain, Open Drain
- Reset:
- Active High/Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
X40420S14I-B FAQ
1.How can I place an order for X40420S14I-B through Aetrix?
Please submit a Request for Quotation (RFQ) for X40420S14I-B on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X40420S14I-B reliable?
The price and inventory of X40420S14I-B are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X40420S14I-B is usually 5 days.
3.What payment methods are accepted for X40420S14I-B?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X40420S14I-B transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X40420S14I-B?
X40420S14I-B orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X40420S14I-B order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X40420S14I-B?
For technical support, including X40420S14I-B datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X40420S14I-B requirements.
6.How does Aetrix verify that X40420S14I-B is sourced from the original manufacturer or authorized distributors?
All X40420S14I-B products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X40420S14I-B meets industry standards.
7.What is the process for return or replacement of X40420S14I-B?
All X40420S14I-B units undergo pre-shipment inspection (PSI). If there is an issue with X40420S14I-B, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X40420S14I-B part is unused and in its original packaging.
Return procedure for X40420S14I-B:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X40420S14I-B Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

