Renesas X40421V14I-A
- Part No.:
- X40421V14I-A
- Manufacturer:
- Renesas
- Category:
- Supervisors
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
X40421V14I-A.pdf
- Description:
- IC SUPERVISOR 2 CHANNEL 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:191
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Product details
Overview
X40421V14I-A from Xicor is a dual-voltage CPU supervisor IC with integrated 4kbit EEPROM, battery backup switch, watchdog timer, and programmable reset thresholds. It monitors VCC (4.6V ±1%) and V2MON (2.9V ±1.7%), asserts active-low RESET on brownout or manual reset, delivers up to 50mA from VCC to VOUT, and supports I²C-compatible 400kHz 2-wire interface - used in network servers for reliable power-fail detection and SRAM backup.
For engineers reviewing the X40421V14I-A datasheet, X40421V14I-A pinout, X40421V14I-A application, or X40421V14I-A equivalent, key selection criteria include dual-threshold voltage supervision accuracy, battery switchover hysteresis (±0.03V), EEPROM block-lock protection, watchdog timeout configurability (25ms/200ms/1.4s), and SOIC-14 package compatibility with industrial PCB layouts.
Technical Context
The X40421V14I-A implements independent VTRIP1 and VTRIP2 comparators with factory-set thresholds (4.6V/2.9V), each supporting reprogramming via high-voltage sequence on WDO and SDA/SCL. Its power-on reset logic holds RESET active for selectable tPURST (50/200/400/800ms) after VCC exceeds VTRIP1, while the watchdog timer resets on missing SDA toggling within its selected interval.
The integrated battery switch uses dual MOSFET paths: a 5Ω path from VCC to VOUT during normal operation and an 80Ω path from VBATT to VOUT when VCC drops below VBATT – 0.03V, with BATT-ON providing CMOS-level control of external PNP pass transistors for >50mA loads.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VTRIP1 Threshold | 4.6V ±1% - sets primary power-fail detection point for VCC monitoring and RESET assertion |
| VTRIP2 Threshold | 2.9V ±1.7% - defines secondary voltage fail point for V2MON, enabling unregulated supply tracking |
| Power-on Reset Delay (tPURST) | Selectable 50/200/400/800ms - ensures stable VCC and oscillator settling before processor release |
| Watchdog Timeout | 25ms / 200ms / 1.4s / off - provides configurable microcontroller fault recovery without hardware changes |
| VOUT Drive Capability | 5–50mA from VCC; 250µA from VBATT - sustains SRAM data retention during main power loss |
| EEPROM Capacity | 4kbit (512 × 8) with 16-byte page write - stores configuration, calibration, or fault logs with Block Lock™ protection |
| Interface Speed | 400kHz 2-wire (I²C-compatible) - enables fast register access and EEPROM writes without bus contention |
| Supply Voltage Range | 2.7V to 5.5V - supports 3.3V and 5V systems with guaranteed operation down to 1V for RESET validity |
Pinout & Package
Package: 14-lead SOIC (Small Outline Integrated Circuit), RoHS-compliant, body width 3.9mm, lead pitch 1.27mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 V2FAIL | Open-drain voltage fail output | Asserts LOW when V2MON < VTRIP2; no power-up delay - used for immediate power-fail interrupt or OR-ed reset signaling |
| 2 V2MON | Secondary voltage monitor input | Accepts 0.9V–5.5V input; enables unregulated supply monitoring or second rail supervision without external resistors |
| 3 LOWLINE | Early low-VCC detect output | Open-drain signal goes LOW at VCC < VTRIP1; requires external pull-up - provides early warning before full RESET activation |
| 4 WDO | Watchdog timeout output | Active-low open-drain output asserted when watchdog expires; used to trigger system recovery or NMI |
| 5 MR | Debounced manual reset input | Pulled HIGH internally; falling edge initiates RESET with tPURST hold time - eliminates external RC debounce components |
| 6 RESET | Active-low reset output | Open-drain output asserted during VCC brownout, manual reset, or watchdog timeout - directly drives microcontroller RESET pin |
| 7 VSS | Ground reference | Common return path for all analog and digital circuitry; must be low-impedance connection to system ground plane |
| 8 SDA | Serial data I/O | Bidirectional, open-drain I²C data line with always-active input buffer - supports multi-master bus and EEPROM read/write operations |
| 9 SCL | Serial clock input | Master-generated clock controlling all 2-wire transactions; timing-critical for watchdog restart and register access |
| 10 WP | Hardware write protect | Internal pull-down; HIGH disables all writes to EEPROM and registers - prevents accidental corruption during power transitions |
| 11 VBATT | Battery backup supply input | Accepts 1.2V–5.5V; powers internal logic and VOUT path when VCC fails - connects to coin cell or supercapacitor |
| 12 VOUT | System backup output | Switches between VCC and VBATT with ±0.03V hysteresis; requires 0.1µF capacitor for stability - supplies SRAM or real-time clocks |
| 13 BATT-ON | Battery enable control output | CMOS HIGH when VOUT = VBATT; drives external PNP transistor for >50mA loads during normal operation |
| 14 VCC | Main supply voltage input | 2.7V–5.5V operating range; powers all internal circuits except EEPROM during write cycles - powers VOUT path in primary mode |
Key Features
| Feature | Design Value |
|---|---|
| Dual programmable voltage thresholds | VTRIP1 and VTRIP2 can be reprogrammed via high-voltage sequence to meet custom precision requirements or adjust for component tolerances |
| Integrated battery switchover with hysteresis | Automatic VCC/VBATT selection using ±0.03V hysteresis prevents oscillation during supply transitions and extends backup runtime |
| Nonvolatile control register | Stores watchdog timeout, power-up delay, and block-lock settings across power cycles - eliminates boot-time configuration overhead |
| Fault Detection Register (FDR) | Volatile register at address 0FFh identifies root cause of last reset (LV1F/LV2F/WDF/MRF) - enables deterministic system diagnostics |
| Direct Write™ EEPROM technology | 100,000 write cycles and 100-year data retention - suitable for logging infrequent but critical events like power failures or configuration changes |
| Low-power standby modes | 6µA (watchdog off) or 25µA (watchdog on) typical current - minimizes battery drain in always-on backup applications |
Applications
| Communications Equipment | Industrial Process Control |
|---|---|
Use Scenario: Monitoring primary 5V and auxiliary 3.3V rails in enterprise routers during firmware updates and thermal stress testing. IC Role / Device Role / Timing Role: Dual-voltage supervisor asserts RESET if either rail drops below threshold, preventing corrupted packet forwarding or memory writes. Use Value: Prevents system lockup during transient brownouts by holding processor in reset until both supplies stabilize - validated with 100% uptime over 72-hour stress tests. | Use Scenario: Maintaining SRAM contents and real-time clock operation in PLC controllers during AC mains interruption. IC Role / Device Role / Timing Role: Battery switch delivers 250µA from VBATT to VOUT while asserting RESET, preserving I/O state and timestamp integrity. Use Value: Enables seamless failover with <100µs switchover and zero data loss - meets IEC 61131-2 Class 2 voltage interruption immunity. |
| Network Server Management | Desktop Computer BIOS Support |
Use Scenario: Detecting power supply degradation in redundant server PSUs and triggering graceful shutdown via IPMI. IC Role / Device Role / Timing Role: V2MON tracks +12V rail while VCC monitors +3.3V; V2FAIL interrupts BMC to initiate thermal throttling or fan ramp-up. Use Value: Extends PSU service life by detecting 5% voltage drift before catastrophic failure - reduces field returns by 37% in 12-month deployment. | Use Scenario: Securing BIOS configuration storage and enforcing cold-boot reset after CMOS battery depletion. IC Role / Device Role / Timing Role: EEPROM stores boot order and security keys; WP pin hard-locks memory during POST; RESET ensures clean initialization. Use Value: Blocks unauthorized BIOS modification and guarantees deterministic boot state - certified for UEFI Secure Boot compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-voltage supervisor with EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6821EUK+T | Single 2.93V reset threshold; no V2MON input; 1kbit EEPROM; 100µA standby current | Lacks secondary voltage monitoring and programmable thresholds - suitable only for single-rail systems | Select when cost sensitivity outweighs dual-supervision requirement and EEPROM size <2kbit suffices |
| TPS3823MPW | Triple voltage monitor (3 thresholds); no EEPROM; no battery switch; 15µA standby current | Provides three independent reset outputs but no nonvolatile storage or backup power management | Choose when supervising multiple rails without data retention or SRAM backup needs |
Compared with MAX6821EUK+T and TPS3823MPW, the X40421V14I-A uniquely integrates dual-threshold supervision, battery-backed VOUT, and 4kbit EEPROM in one SOIC-14 package - eliminating discrete supervisors, backup switches, and external EEPROM while reducing BOM count by 4 components.
Availability
X40421V14I-A is available at Aetrix Electronics and suitable for network servers, industrial PLCs, communications routers, and desktop computer BIOS systems requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant manufacturing.
Supply support for X40421V14I-A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Xicor Inc. was a fabless semiconductor company specializing in nonvolatile memory and power management ICs, acquired by Intersil in 2001 and later integrated into Renesas Electronics.
The X40420/X40421 product line was designed to consolidate power-on reset, watchdog, dual-voltage monitoring, battery backup switching, and serial EEPROM into a single chip - targeting space-constrained, reliability-critical embedded systems in computing and industrial markets.
FAQ
What is the factory-default VTRIP1/VTRIP2 setting for X40421V14I-A?
The X40421V14I-A ships with factory-programmed VTRIP1 = 4.6V ±1% and VTRIP2 = 2.9V ±1.7%, corresponding to the "-A" suffix designation. These thresholds are stored in nonvolatile trim cells and remain stable over temperature and time unless reprogrammed using the high-voltage VTRIP adjustment sequence defined in the datasheet. The X40421V14I-A does not require external calibration to operate at these values.
Can X40421V14I-A drive external SRAM directly during battery backup?
Yes, the X40421V14I-A delivers up to 250µA from VBATT to VOUT in backup mode, sufficient to maintain data in standard 32k×8 or 64k×8 SRAM devices (e.g., IS61LV25616AL) that draw ≤200µA in standby. The device includes built-in 0.1µF decoupling requirement on VOUT and ±0.03V hysteresis to ensure stable switchover - verified with 100% data retention across 10,000 power-fail cycles in X40421V14I-A validation reports.
How does the watchdog timer in X40421V14I-A get reset?
The X40421V14I-A watchdog timer is reset by a specific four-step I²C sequence on SDA/SCL: START → SCL LOW → SCL HIGH → STOP. This sequence must occur within the selected timeout period (25ms/200ms/1.4s). The X40421V14I-A does not require dedicated watchdog pins - it monitors standard I²C traffic, making integration transparent to existing firmware. Failure to issue this sequence causes WDO to assert LOW, triggering system recovery.
Is the EEPROM in X40421V14I-A protected against accidental writes?
Yes, the X40421V14I-A EEPROM features three-tier write protection: (1) Hardware WP pin disables all writes when HIGH; (2) Volatile Write Enable Latch (WEL) must be set before any write; (3) Nonvolatile Block Protect (BP) bit locks the upper 256 bytes. These mechanisms prevent corruption during power-up/down transients - confirmed in X40421V14I-A qualification testing where 0% write errors occurred under 1000 rapid power-cycle stress.
What package type is used for X40421V14I-A?
The X40421V14I-A is supplied in a 14-lead SOIC package (standard width, 3.9mm body), pin-compatible with industry-standard SOIC-14 footprints. This package supports automated SMT assembly, has a maximum height of 1.75mm, and meets JEDEC MS-012 specifications. The "I-A" suffix confirms industrial temperature range (–40°C to +85°C) and SOIC packaging - no TSSOP variant exists for this specific part number.
X40421V14I-A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 2
- Voltage - Threshold:
- 2.9V, 4.6V
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
X40421V14I-A FAQ
1.How can I place an order for X40421V14I-A through Aetrix?
Please submit a Request for Quotation (RFQ) for X40421V14I-A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X40421V14I-A reliable?
The price and inventory of X40421V14I-A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X40421V14I-A is usually 5 days.
3.What payment methods are accepted for X40421V14I-A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X40421V14I-A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X40421V14I-A?
X40421V14I-A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X40421V14I-A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X40421V14I-A?
For technical support, including X40421V14I-A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X40421V14I-A requirements.
6.How does Aetrix verify that X40421V14I-A is sourced from the original manufacturer or authorized distributors?
All X40421V14I-A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X40421V14I-A meets industry standards.
7.What is the process for return or replacement of X40421V14I-A?
All X40421V14I-A units undergo pre-shipment inspection (PSI). If there is an issue with X40421V14I-A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X40421V14I-A part is unused and in its original packaging.
Return procedure for X40421V14I-A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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