Renesas X9221AYPI
- Part No.:
- X9221AYPI
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 20-DIP (0.300", 7.62mm)
- Datasheet:
-
X9221AYPI.pdf
- Description:
- IC DGTL POT 2KOHM 64TAP 20DIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,641
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X9221AYPI from Intersil is a dual digitally controlled potentiometer (XDCP™) with 64-tap resolution per channel, 2-wire I²C-compatible serial interface, and nonvolatile storage of four wiper positions per pot. It operates at 5V ±10%, supports industrial temperature range (–40°C to +85°C), and functions as a precision programmable resistor in analog signal conditioning circuits.
For engineers reviewing the X9221AYPI datasheet, X9221AYPI pinout, X9221AYPI application, or X9221AYPI equivalent, this device serves as a drop-in replacement for mechanical potentiometers in closed-loop gain control, offset trimming, and programmable voltage divider designs requiring EEPROM-backed settings and I²C configurability.
Technical Context
The X9221AYPI integrates two independent 63-element resistor arrays with decoded 6-bit wiper counter registers (WCR), each backed by four nonvolatile data registers (DR0–DR3). Wiper position is controlled via I²C commands including direct write, register transfer, and real-time increment/decrement modes.
Its 2-wire interface complies with standard I²C timing (fSCL ≤ 100 kHz), supports slave address configuration via A0–A3 pins, and features acknowledge polling during 10 ms nonvolatile writes. Power-up automatically loads DR0 into each WCR, ensuring repeatable startup behavior without host intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Dual digitally controlled potentiometer (XDCP™) with volatile wiper control and nonvolatile register storage |
| Resolution | 64 taps per potentiometer - enables 1.56% step resolution across full resistance range |
| Total Resistance | 10 kΩ - matched end-to-end resistance for both pots; supports ±20% tolerance and 50 mW power rating per channel |
| Interface | 2-wire I²C-compatible bus - uses SCL/SDA with configurable 7-bit slave address (0101xxxxB) |
| Nonvolatile Endurance | 100,000 writes per bit per register - sufficient for field calibration cycles and firmware-based trim updates |
| Operating Temp | –40°C to +85°C - qualified for industrial-grade embedded systems and instrumentation applications |
| Supply Voltage | 5 V ±10% - compatible with standard logic rails; requires stable VCC ramp rate (0.2–50 V/ms) |
Pinout & Package
Package: 20-lead plastic DIP (PDIP), 0.300" wide, RoHS-compliant (Pb-free anneal finish), MDP0031 package drawing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 | VH0/RH0, VL0/RL0, VW0/RW0, A0–A3 | Pot 0 high/low/wiper terminals and 4-bit I²C address inputs - configure unique slave address on shared bus |
| 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 | VW1/RW1, VL1/RL1, VH1/RH1, SCL, SDA, VSS, VCC, RES, RES, RES | Pot 1 terminals, serial clock/data lines, ground/power, and three reserved pins - RES pins must remain unconnected |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent XDCP channels | Enables simultaneous gain/offset control in stereo audio or dual-sensor signal chains without inter-channel crosstalk |
| Four nonvolatile data registers per pot | Stores factory calibrations, user presets, or backup values - eliminates need for external EEPROM in trimming applications |
| Real-time wiper increment/decrement mode | Allows host microcontroller to adjust resistance in single-tap steps via clocked SCL pulses - ideal for fine-tuning UI controls |
| Power-up auto-load from DR0 | Guarantees known wiper state at boot without host initialization sequence - critical for fail-safe analog subsystems |
| I²C register-oriented command set | Supports read/write of wiper position and data registers, plus global transfers - simplifies firmware driver development |
Applications
| Audio Level Control | DC Offset Calibration |
|---|---|
|
Use Scenario: Programmable volume control in professional audio mixers with recallable channel settings. IC Role / Device Role / Timing Role: Dual-channel digital potentiometer implementing left/right channel attenuation with independent wiper positioning. Use Value: Replaces dual-gang mechanical pots; retains last-set levels across power cycles using nonvolatile DR0 storage. |
Use Scenario: Precision null adjustment in strain gauge amplifier front-ends for load cell measurement systems. IC Role / Device Role / Timing Role: Two-terminal variable resistor injecting calibrated offset current into op-amp summing junction. Use Value: Enables automated factory calibration via I²C; stores multiple trim points (DR0–DR3) for sensor-specific compensation. |
| Programmable Gain Amplifier | Temperature-Compensated Reference |
|
Use Scenario: Digitally adjustable gain stage in medical ECG signal conditioning where gain must be reconfigured per patient protocol. IC Role / Device Role / Timing Role: Three-terminal potentiometer configuring feedback network of instrumentation amplifier. Use Value: Provides 64-step gain resolution (≈0.1 dB/step at mid-range); wiper response time <1 ms ensures rapid reconfiguration. |
Use Scenario: Compensation network in precision voltage reference ICs to correct for thermal drift over –40°C to +85°C. IC Role / Device Role / Timing Role: Dual-potentiometer forming ratio-metric divider that adjusts reference output based on temperature sensor feedback. Use Value: Leverages 200 ppm/°C radiometric tempco spec to maintain <0.5% output error across full industrial temperature range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ10 | Single 256-tap channel, I²C interface, 10 kΩ, ±30% RTOL, no global transfer instructions | Lacks dual-channel integration; requires two devices for same functionality as X9221AYPI | Select when higher resolution (256 taps) is prioritized over channel density and register flexibility |
| MCP42010-I/P | Dual 256-tap SPI interface, 10 kΩ, ±20% RTOL, volatile-only wiper memory, no nonvolatile registers | Requires external MCU to store settings; no DR0 auto-load on power-up | Select when SPI-native systems exist and nonvolatile storage is handled externally or not required |
Compared with AD5242BRUZ10 and MCP42010-I/P, the X9221AYPI uniquely delivers dual-channel operation with on-chip nonvolatile register storage, I²C register-oriented command architecture, and power-up DR0 auto-load - reducing BOM count and eliminating boot-time host initialization overhead.
Availability
X9221AYPI is available at Aetrix Electronics and suitable for industrial instrumentation, medical signal conditioning, and programmable power supply design requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for X9221AYPI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) is a U.S.-based semiconductor company specializing in precision analog and power management ICs for industrial, communications, and computing markets.
The X9221A product line was designed specifically for replacing mechanical potentiometers in digitally calibrated analog systems - emphasizing nonvolatile setting retention, I²C configurability, and dual-channel integration in compact DIP/SOIC packages.
FAQ
What is the total resistance value and tolerance of the X9221AYPI?
The X9221AYPI has a nominal total resistance of 10 kΩ with a tolerance of ±20% across the full operating temperature range. This value is specified in the Ordering Information table and confirmed in the Analog Characteristics section of the FN8163 datasheet. The resistance remains stable under 50 mW per potentiometer at +25°C, and the device maintains linearity within ±1 MI absolute and ±0.2 MI relative error bands.
Does the X9221AYPI support I²C standard-mode or fast-mode timing?
The X9221AYPI supports standard-mode I²C operation up to 100 kHz maximum clock frequency (fSCL), with minimum tLOW = 4700 ns and tHIGH = 4000 ns. It does not support fast-mode (400 kHz) or high-speed mode. These timing parameters are fully specified in the AC Characteristics table (Page 12) and validated across the industrial temperature range (–40°C to +85°C).
How many nonvolatile registers does the X9221AYPI provide per potentiometer?
The X9221AYPI provides four nonvolatile data registers (DR0–DR3) per potentiometer, totaling eight nonvolatile registers. Each register can store a 6-bit wiper position value. DR0 is automatically loaded into the corresponding wiper counter register (WCR) at power-up, while DR1–DR3 require explicit transfer commands (XFR Data Register to WCR) to affect wiper position.
What is the wiper response time after issuing a STOP condition for the X9221AYPI?
The wiper response time after generating a STOP condition is 1000 µs maximum (tSTPWV), as specified in the AC Characteristics table (Page 12). This delay reflects the time required for the internal switch matrix to settle after a write command completes. For real-time adjustments, the Increment/Decrement mode offers sub-microsecond per-step response synchronized to SCL edges.
Can the X9221AYPI operate from a 3.3 V supply?
No, the X9221AYPI is specified only for 5 V ±10% operation (4.5 V to 5.5 V), as stated in the Recommended Operating Conditions table (Page 9). Supplying 3.3 V falls outside the valid VCC range and will result in undefined behavior, including failure to recognize I²C start conditions, incorrect wiper positioning, or inability to execute nonvolatile writes. A level-shifting interface does not resolve the core VCC requirement.
X9221AYPI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 20-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 64
- Resistance (Ohms):
- 2k
- Interface:
- I2C
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±300ppm/°C
- Mounting Type:
- Through Hole
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-PDIP
- Operating Temperature:
- -40°C ~ 85°C
- Resistance - Wiper (Ohms) (Typ):
- 40
X9221AYPI FAQ
1.How can I place an order for X9221AYPI through Aetrix?
Please submit a Request for Quotation (RFQ) for X9221AYPI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X9221AYPI reliable?
The price and inventory of X9221AYPI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X9221AYPI is usually 5 days.
3.What payment methods are accepted for X9221AYPI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X9221AYPI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X9221AYPI?
X9221AYPI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X9221AYPI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X9221AYPI?
For technical support, including X9221AYPI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X9221AYPI requirements.
6.How does Aetrix verify that X9221AYPI is sourced from the original manufacturer or authorized distributors?
All X9221AYPI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X9221AYPI meets industry standards.
7.What is the process for return or replacement of X9221AYPI?
All X9221AYPI units undergo pre-shipment inspection (PSI). If there is an issue with X9221AYPI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X9221AYPI part is unused and in its original packaging.
Return procedure for X9221AYPI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X9221AYPI Tags

-
MCP4018T-103E/LT
Microchip Technology

-
MCP4018T-503E/LT
Microchip Technology

-
MCP4011T-103E/SN
Microchip Technology

-
MCP4018T-104E/LT
Microchip Technology

-
MCP4017T-503E/LT
Microchip Technology

-
MCP4018T-502E/LT
Microchip Technology

-
MCP4017T-103E/LT
Microchip Technology

-
MCP4531T-103E/MF
Microchip Technology

-
MCP4021T-202E/SN
Microchip Technology

-
MCP4023T-103E/CH
Microchip Technology

-
MCP4022T-503E/CH
Microchip Technology

-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

