Renesas X9250TS24IZ-2.7T2
- Part No.:
- X9250TS24IZ-2.7T2
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 24-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
X9250TS24IZ-2.7T2.pdf
- Description:
- IC DGT POT 100KOHM 256TAP 24SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,196
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X9250TS24IZ-2.7T2 from Intersil is a quad digitally controlled potentiometer (XDCP™) with 256-tap resolution per channel, SPI serial interface, and dual analog supply rails (V+ = +2.7V to +5.5V, V− = −2.7V to −5.5V). It integrates four independent 100kΩ potentiometers in a single 24-lead SOIC package, supporting precision voltage divider, gain/offset adjustment, and programmable biasing in mixed-signal systems.
For engineers reviewing the X9250TS24IZ-2.7T2 datasheet, X9250TS24IZ-2.7T2 pinout, X9250TS24IZ-2.7T2 application, or X9250TS24IZ-2.7T2 equivalent, key selection criteria include its −2.7V to +5.5V analog supply range, nonvolatile wiper position storage across four data registers per pot, 40Ω typical wiper resistance at 5V, and support for industrial temperature operation (−40°C to +85°C).
Technical Context
The X9250TS24IZ-2.7T2 implements four independent resistor arrays-each with 255 segments and 256 tap points-controlled by dedicated 8-bit volatile Wiper Counter Registers (WCRs). Each array connects to VH/RH, VL/RL, and VW/RW terminals, enabling three-terminal potentiometer or two-terminal variable resistor configurations.
It uses standard SPI protocol (CS, SCK, SI, SO) with device addressing via A0/A1 pins, hardware write protection via WP, and communication pause capability via HOLD. Nonvolatile storage supports 100,000 write cycles per register bit and 100-year data retention, with power-up auto-recall of DR0 contents to each WCR.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 100kΩ per potentiometer - defines full-scale voltage division ratio and current limiting capability in bias/gain networks. |
| Resolution | 256 taps (0.4% step size) - enables fine-grained analog tuning with ±1 MI absolute linearity error. |
| Analog Supply Range | V+ = +2.7V to +5.5V; V− = −2.7V to −5.5V - supports bipolar signal conditioning and rail-to-rail wiper swing in op-amp feedback paths. |
| Wiper Resistance | 40Ω typical at VCC = 5V - minimizes insertion error in low-impedance sensor or amplifier interfaces. |
| Standby Current | <5µA total package - enables ultra-low-power operation in battery-backed or energy-constrained systems. |
| Nonvolatile Endurance | 100,000 data changes per bit - ensures long-term reliability for field-adjustable calibration storage. |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade embedded control and instrumentation environments. |
Pinout & Package
Package: 24-lead SOIC (300 mil), Pb-free, RoHS-compliant (M24.3 drawing).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 SCK | Serial Clock Input | Edge-triggered clock for SPI data transfer; rising edge latches SI, falling edge clocks SO. |
| 2 SI | Serial Data Input | Accepts instruction bytes, addresses, and data; supports daisy-chaining when shared with SO. |
| 3 A0, 4 A1 | Device Address Inputs | Set LSBs of 8-bit slave address; enable up to four X9250 devices on one SPI bus. |
| 5 VH0/RH0–VH3/RH3 | Potentiometer High-Side Terminals | Connect to positive analog rail (V+) or signal source; define upper voltage limit of each resistor array. |
| 6 VL0/RL0–VL3/RL3 | Potentiometer Low-Side Terminals | Connect to negative analog rail (V−) or reference ground; define lower voltage limit of each resistor array. |
| 7 VW0/RW0–VW3/RW3 | Wiper Outputs | Provide adjustable tap voltage/current; output impedance dominated by 40Ω typical wiper resistance. |
| 8 WP | Hardware Write Protect | Active-low input blocking nonvolatile writes to Data Registers; prevents accidental configuration loss. |
| 9 V+, 10 V− | Analog Power Supplies | Independent dual-rail supplies for XDCP core; must be stable within 1ms of each other at power-up. |
| 11 VCC, 12 VSS | Digital Supply & Ground | Power digital logic (SPI interface, control circuitry); VCC = 2.7V to 5.5V, compatible with 3.3V/5V systems. |
| 13 CS | Chip Select | Active-low enable; high-impedance SO and standby mode when deasserted; required HIGH→LOW transition before first command. |
| 14 HOLD | Communication Pause | Pauses ongoing SPI transaction without resetting state; requires SCK LOW during assertion/deassertion. |
| 15–24 | No Connection / Reserved | NC pins (15, 16, 19–24); unused in this variant; must remain unconnected per datasheet. |
Key Features
| Feature | Design Value |
|---|---|
| Quad 256-tap XDCP arrays | Four independent, software-controlled potentiometers replace mechanical trimmers and reduce BOM count in multi-channel systems. |
| Nonvolatile wiper storage (4× DR) | Each pot retains four user-defined settings across power cycles, enabling factory calibration, user presets, and fail-safe defaults. |
| SPI-compatible serial interface | Standard 4-wire interface (CS/SCK/SI/SO) with addressable multi-device support simplifies microcontroller integration and PCB routing. |
| Bipolar analog supply capability | V+ and V− rails allow direct use in AC-coupled, dual-supply op-amp circuits without level-shifting or external bias networks. |
| Low-power standby mode | <5µA total quiescent current extends battery life in portable test equipment and remote sensors. |
| Industrial temperature rating | −40°C to +85°C operation ensures stable performance in automotive ECUs, industrial PLCs, and outdoor instrumentation. |
Applications
| Audio Signal Processing | Programmable Power Supply |
|---|---|
|
Use Scenario: Adjusting gain and offset in multi-channel audio codec front-ends with automatic calibration. IC Role / Device Role / Timing Role: Quad XDCP acts as digitally tuned voltage dividers in op-amp feedback loops and bias networks for microphone preamps and line drivers. Use Value: Eliminates manual trimming, enables firmware-based recalibration, and maintains 0.4% resolution across temperature without drift. |
Use Scenario: Setting precise output voltage and current limits in programmable DC bench supplies. IC Role / Device Role / Timing Role: Configures reference divider ratios for voltage feedback and current sense amplifiers in closed-loop SMPS controllers. Use Value: Supports 100kΩ high-impedance sensing with <40Ω wiper resistance, minimizing loading error in precision reference paths. |
| Sensor Calibration Module | Industrial Analog I/O |
|
Use Scenario: Compensating for offset and span errors in RTD, thermocouple, and bridge sensor signal chains. IC Role / Device Role / Timing Role: Provides nonvolatile, field-updatable gain/offset correction in analog front-end (AFE) stages before ADC conversion. Use Value: Stores four calibration points per channel (DR0–DR3), enabling multi-point linearization and sensor-specific profiles. |
Use Scenario: Configuring input scaling and output drive levels in modular PLC analog I/O cards. IC Role / Device Role / Timing Role: Acts as programmable termination resistors and level-setting elements for 4–20mA loop drivers and voltage-input receivers. Use Value: Dual-rail (±2.7V to ±5.5V) operation supports bipolar 10V and ±5V industrial standards without external level shifters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ100 | Single 256-tap 100kΩ pot; I²C interface; no dual-rail analog supply; 24-lead TSSOP only. | Lacks quad integration and bipolar analog capability; suitable for simpler, cost-sensitive designs with I²C infrastructure. | Select when board space permits discrete pots and system uses I²C instead of SPI. |
| MCP42010-I/P | Dual 256-tap 10kΩ pot; SPI interface; single 2.7–5.5V supply; no V+/V− rails; DIP-14 package. | Lower resistance value and unipolar supply limit use in high-impedance or bipolar signal paths; lacks nonvolatile DR0 auto-recall. | Choose for legacy through-hole designs requiring dual pots but not bipolar operation or industrial temp range. |
Compared with AD5242BRUZ100 and MCP42010-I/P, the X9250TS24IZ-2.7T2 uniquely delivers quad-channel control, true bipolar analog operation, and industrial-grade nonvolatile storage-making it optimal for compact, high-reliability mixed-signal calibration systems where SPI is available and supply flexibility is critical.
Availability
X9250TS24IZ-2.7T2 is available at Aetrix Electronics and suitable for industrial automation, precision instrumentation, and programmable power supply applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for X9250TS24IZ-2.7T2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil (now part of Renesas Electronics) is a semiconductor company specializing in precision analog, power management, and interface ICs for industrial, communications, and computing markets.
The X9250 series was designed as a drop-in replacement for mechanical potentiometers in digitally calibrated systems-emphasizing nonvolatile configuration, SPI simplicity, and robust analog performance across extended temperature ranges.
FAQ
What is the analog supply voltage range supported by the X9250TS24IZ-2.7T2?
The X9250TS24IZ-2.7T2 supports V+ = +2.7V to +5.5V and V− = −2.7V to −5.5V, enabling true bipolar operation. This allows the device to function in AC-coupled circuits, dual-supply op-amp configurations, and precision offset adjustment without external level-shifting components. The "-2.7" suffix explicitly denotes this extended low-voltage analog rail capability.
How does nonvolatile storage work in the X9250TS24IZ-2.7T2?
The X9250TS24IZ-2.7T2 provides four 8-bit nonvolatile Data Registers (DR0–DR3) per potentiometer. Writes to these registers trigger an internal 5–10ms high-voltage programming cycle, confirmed via the Read Status command's WIP bit. On power-up, DR0 automatically loads into the corresponding volatile Wiper Counter Register (WCR), ensuring repeatable startup behavior without host intervention.
Can the X9250TS24IZ-2.7T2 be used as a two-terminal variable resistor?
Yes, the X9250TS24IZ-2.7T2 supports two-terminal operation by connecting either VH/RH or VL/RL to a fixed potential and using VW/RW with the remaining terminal. Its 40Ω typical wiper resistance and 100kΩ end-to-end resistance make it suitable for current-limiting, bias adjustment, and programmable load applications-provided wiper current stays within ±7.5mA limits.
What is the purpose of the HOLD pin on the X9250TS24IZ-2.7T2?
The HOLD pin pauses ongoing SPI communication without resetting the instruction sequence. When asserted LOW while SCK is LOW, it freezes data transfer; returning HOLD HIGH (with SCK still LOW) resumes from the exact point of interruption. This feature is valuable in real-time systems where host MCU interrupts must temporarily suspend potentiometer reconfiguration without losing context.
Does the X9250TS24IZ-2.7T2 require specific power supply sequencing?
No strict sequencing is required for VCC, V+, and V−, but all three must reach final values within 1ms of each other. During ramp-up, voltages on VH/RH, VL/RL, and VW/RW pins must remain between V− and V+ at all times. Wiper position recall from nonvolatile memory only occurs after all supplies stabilize-ensuring deterministic startup behavior in complex power domains.
X9250TS24IZ-2.7T2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 24-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 4
- Number of Taps:
- 256
- Resistance (Ohms):
- 100k
- Interface:
- SPI
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- ±2.7V ~ 5.5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±300ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-SOIC
- Operating Temperature:
- -40°C ~ 85°C
- Resistance - Wiper (Ohms) (Typ):
- 150
X9250TS24IZ-2.7T2 FAQ
1.How can I place an order for X9250TS24IZ-2.7T2 through Aetrix?
Please submit a Request for Quotation (RFQ) for X9250TS24IZ-2.7T2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X9250TS24IZ-2.7T2 reliable?
The price and inventory of X9250TS24IZ-2.7T2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X9250TS24IZ-2.7T2 is usually 5 days.
3.What payment methods are accepted for X9250TS24IZ-2.7T2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X9250TS24IZ-2.7T2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X9250TS24IZ-2.7T2?
X9250TS24IZ-2.7T2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X9250TS24IZ-2.7T2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X9250TS24IZ-2.7T2?
For technical support, including X9250TS24IZ-2.7T2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X9250TS24IZ-2.7T2 requirements.
6.How does Aetrix verify that X9250TS24IZ-2.7T2 is sourced from the original manufacturer or authorized distributors?
All X9250TS24IZ-2.7T2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X9250TS24IZ-2.7T2 meets industry standards.
7.What is the process for return or replacement of X9250TS24IZ-2.7T2?
All X9250TS24IZ-2.7T2 units undergo pre-shipment inspection (PSI). If there is an issue with X9250TS24IZ-2.7T2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X9250TS24IZ-2.7T2 part is unused and in its original packaging.
Return procedure for X9250TS24IZ-2.7T2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X9250TS24IZ-2.7T2 Tags

-
MCP4018T-103E/LT
Microchip Technology

-
MCP4018T-503E/LT
Microchip Technology

-
MCP4011T-103E/SN
Microchip Technology

-
MCP4018T-104E/LT
Microchip Technology

-
MCP4017T-503E/LT
Microchip Technology

-
MCP4018T-502E/LT
Microchip Technology

-
MCP4017T-103E/LT
Microchip Technology

-
MCP4531T-103E/MF
Microchip Technology

-
MCP4021T-202E/SN
Microchip Technology

-
MCP4023T-103E/CH
Microchip Technology

-
MCP4022T-503E/CH
Microchip Technology

-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

