Renesas X9250US24Z
- Part No.:
- X9250US24Z
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 24-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
X9250US24Z.pdf
- Description:
- IC DGTL POT 50KOHM 256TAP 24SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:746
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X9250US24Z from Intersil is a quad digitally controlled potentiometer (XDCP™) with 256-tap resolution per channel, SPI serial interface, and dual ±2.7V to ±5.5V analog supplies (V+/V−), operating from 0°C to +70°C in 24-lead SOIC. It integrates four independent 50kΩ potentiometers with nonvolatile wiper position storage, <5µA standby current, and 40Ω typical wiper resistance at 5V - used for precision gain/offset trimming in programmable power supplies and sensor signal conditioning.
For engineers reviewing the X9250US24Z datasheet, X9250US24Z pinout, X9250US24Z application, or X9250US24Z equivalent, key selection considerations include its 50kΩ end-to-end resistance, RoHS-compliant Pb-free SOIC-24 package, hardware write-protect (WP) pin, HOLD functionality for SPI pause/resume, and support for dual-supply operation down to ±2.7V.
Technical Context
The X9250US24Z implements four independent 255-segment resistor arrays with CMOS-switched wipers controlled by volatile Wiper Counter Registers (WCRs), each backed by four 8-bit nonvolatile Data Registers (DR0–DR3). Power-up loads DR0 into the corresponding WCR, enabling deterministic startup behavior.
It supports full SPI protocol compliance including read/write WCR and DR instructions, global data transfer, increment/decrement wiper control, and status monitoring via WIP bit. The device requires VCC (2.7V–5.5V), V+ (±2.7V to ±5.5V), and V− supplies, with all pot pins referenced strictly between V− and V+.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Number of pots | Four independent digital potentiometers on single die |
| Resolution | 256 taps (0.4% step resolution); enables 8-bit precision adjustment |
| End-to-end resistance | 50kΩ ±20%; fixed value per channel, suitable for mid-range impedance matching |
| Wiper resistance | 40Ω typical at VCC = 5V; low on-resistance minimizes signal path error in voltage divider use |
| Supply ranges | VCC: 2.7V–5.5V; V+: +2.7V–+5.5V; V−: −2.7V–−5.5V; supports true bipolar analog operation |
| Nonvolatile endurance | 100,000 data changes per bit per register; ensures long-term field reliability for calibration storage |
| Standby current | <5µA total package; critical for battery-powered or low-power system modes |
Pinout & Package
Package: 24-lead SOIC (300 mil), RoHS-compliant Pb-free finish (M24.3 drawing).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 S0 | Serial Output | Data output during read cycles; high-impedance when CS HIGH |
| 2 A0 | Device Address LSB | Configures slave address bits; enables up to 4 devices on shared SPI bus |
| 3 VW3/RW3 | Pot 3 wiper | Variable output terminal for fourth potentiometer array |
| 4 V+ | Analog positive supply | Positive rail for all four potentiometer arrays; must exceed all VH/RH voltages |
| 5 VCC | Digital supply | Power for SPI interface and logic; independent from analog supplies |
| 6 VL0/RL0 | Pot 0 low terminal | Fixed lower end of first potentiometer; referenced to V− |
| 7–10 NC | No connection | Not internally bonded; must be left floating or grounded per layout guidelines |
| 11 VL3/RL3 | Pot 3 low terminal | Fixed lower end of fourth potentiometer; referenced to V− |
| 12 VH0/RH0 | Pot 0 high terminal | Fixed upper end of first potentiometer; referenced to V+ |
| 13 VW0/RW0 | Pot 0 wiper | Adjustable output terminal for first potentiometer array |
| 14 CS | Chip Select | Active-low enable; required HIGH→LOW transition before any SPI operation |
| 15 A1 | Device Address MSB | Second address bit; combines with A0 to set unique SPI slave ID |
| 16 SI | Serial Input | Command/data input; latched on rising SCK edge |
| 17 WP | Hardware Write Protect | LOW disables nonvolatile writes to Data Registers; prevents accidental calibration loss |
| 18 HOLD | SPI communication hold | Pauses ongoing SPI sequence without resetting state; requires SCK LOW during assertion |
| 19 SCK | Serial Clock | Master-generated clock; rising edge latches SI, falling edge clocks SO |
| 20 VL2/RL2 | Pot 2 low terminal | Fixed lower end of third potentiometer; referenced to V− |
| 21 VH2/RH2 | Pot 2 high terminal | Fixed upper end of third potentiometer; referenced to V+ |
| 22 VW2/RW2 | Pot 2 wiper | Adjustable output terminal for third potentiometer array |
| 23 V− | Analog negative supply | Negative rail for all four potentiometer arrays; must be below all VL/RL voltages |
| 24 VSS | Digital ground | Reference for VCC and digital I/O; isolated from analog ground per layout best practice |
Key Features
| Feature | Design Value |
|---|---|
| Quad 256-tap XDCP architecture | Enables simultaneous multi-channel gain/offset tuning in compact space-saving footprint |
| Four nonvolatile Data Registers per pot | Stores up to four distinct calibration points per channel; eliminates external EEPROM |
| SPI-compatible interface with HOLD/CS/WP | Supports robust industrial bus communication with pause capability and hardware write lock |
| Dual-supply analog section (V+/V−) | Allows true bipolar signal conditioning (e.g., ±12V op-amp circuits) without level-shifting |
| 100-year data retention | Guarantees calibration stability over product lifetime without periodic refresh or backup power |
| RoHS-compliant Pb-free SOIC-24 | Meets global environmental standards while maintaining compatibility with legacy reflow profiles |
Applications
| Programmable Power Supply Trim | Sensor Signal Conditioning |
|---|---|
|
Use Scenario: Adjusting feedback resistors in adjustable DC-DC converters or linear regulators to maintain precise output voltage across temperature and load. IC Role / Device Role / Timing Role: Four-channel digital potentiometer providing programmable R1/R2 ratio for voltage reference division and current limit setting. Use Value: Enables factory calibration and field recalibration without soldering; 50kΩ resistance matches common regulator feedback networks. |
Use Scenario: Compensating offset and gain drift in bridge-based pressure or temperature sensors interfaced to instrumentation amplifiers. IC Role / Device Role / Timing Role: Dual-pot configuration for real-time zero and span adjustment in analog front-end signal chains. Use Value: 256-step resolution delivers <±0.5mV offset correction accuracy; nonvolatile storage retains calibrated values after power cycle. |
| Audio Channel Balance Control | Industrial DAC Output Scaling |
|
Use Scenario: Implementing software-controlled left/right channel volume balancing in professional audio mixing consoles or broadcast equipment. IC Role / Device Role / Timing Role: Two independent pots acting as variable attenuators in differential audio paths with matched 50kΩ impedance. Use Value: Low 40Ω wiper resistance preserves high-frequency response; SPI interface allows synchronized multi-channel updates. |
Use Scenario: Scaling full-scale output range of 12-bit DACs to match varying actuator input requirements (e.g., 0–5V, 0–10V, ±10V) in PLC analog outputs. IC Role / Device Role / Timing Role: Three-terminal potentiometer configured as programmable voltage divider to attenuate DAC output before buffer stage. Use Value: Dual-supply operation (±2.7V to ±5.5V) supports bipolar DAC scaling; 100kΩ tolerance ensures stable gain accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5204BRUZ10 | Quad 10kΩ pot; SPI interface; single 2.7–5.5V supply; no dual analog rails | Limited to unipolar analog signals; lower end-to-end resistance reduces loading on high-impedance sources | Select when only unipolar operation is needed and board space permits TSSOP-24 package |
| MCP42050-I/P | Dual 50kΩ pot; SPI interface; single 2.7–5.5V supply; wiper resistance ~120Ω typical | Fewer channels; higher wiper resistance increases gain error in precision dividers | Choose for cost-sensitive dual-channel designs where 100kΩ tolerance and bipolar support are not required |
Compared with AD5204BRUZ10 and MCP42050-I/P, the X9250US24Z uniquely supports true bipolar analog operation with separate V+/V− rails and provides four independent 50kΩ channels in a single SOIC-24 package - making it optimal for industrial sensor interfaces and programmable power supplies requiring calibration persistence and wide supply flexibility.
Availability
X9250US24Z is available at Aetrix Electronics and suitable for programmable power supplies, sensor signal conditioning, audio channel balancing, and industrial DAC output scaling requiring stable component supply and long-term calibration integrity.
Supply support for X9250US24Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil (now part of Renesas Electronics) is a semiconductor company specializing in precision analog, power management, and interface ICs for industrial, communications, and computing markets.
The X9250 series was designed as a family of quad digitally controlled potentiometers targeting high-reliability calibration and trimming applications in programmable analog systems requiring nonvolatile storage and dual-supply operation.
FAQ
What is the maximum operating temperature range for the X9250US24Z?
The X9250US24Z is rated for commercial temperature operation from 0°C to +70°C, as confirmed in the Ordering Information table on page 2 of FN8165 Rev.3.00. This distinguishes it from industrial-grade variants like X9250US24I (−40°C to +85°C) and confirms its suitability for indoor, non-extreme environment applications.
Does the X9250US24Z support true bipolar analog operation?
Yes, the X9250US24Z supports true bipolar analog operation via dedicated V+ and V− pins, each rated from ±2.7V to ±5.5V. All potentiometer terminals (VH/RH, VL/RL, VW/RW) must remain within this V− to V+ range, enabling direct use in ±12V op-amp circuits and other bipolar signal paths without external level-shifting circuitry.
How many nonvolatile registers does each potentiometer in the X9250US24Z have?
Each of the four potentiometers in the X9250US24Z has four 8-bit nonvolatile Data Registers (DR0 through DR3), as specified in the Device Description section (page 4) and Figure 1. These registers retain wiper positions and system parameters for up to 100 years and support direct read/write and global transfer operations.
What is the purpose of the HOLD pin on the X9250US24Z?
The HOLD pin on the X9250US24Z pauses ongoing SPI communication without resetting the command sequence. When asserted LOW while SCK is LOW, it freezes data transfer; returning HOLD HIGH (with SCK still LOW) resumes operation. This feature enables priority interrupt handling in microcontroller systems without losing synchronization with the X9250US24Z.
Can the X9250US24Z be used as a two-terminal variable resistor?
Yes, the X9250US24Z can be configured as a two-terminal variable resistor by connecting either VH/RH or VL/RL to the wiper (VW/RW) terminal, as explicitly stated in the DESCRIPTION section (page 1). This mode is commonly used for programmable current limiting or adjustable biasing where only resistance variation-not voltage division-is required.
X9250US24Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 24-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 4
- Number of Taps:
- 256
- Resistance (Ohms):
- 50k
- Interface:
- SPI
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- ±5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±300ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-SOIC
- Operating Temperature:
- 0°C ~ 70°C
- Resistance - Wiper (Ohms) (Typ):
- 150
X9250US24Z FAQ
1.How can I place an order for X9250US24Z through Aetrix?
Please submit a Request for Quotation (RFQ) for X9250US24Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X9250US24Z reliable?
The price and inventory of X9250US24Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X9250US24Z is usually 5 days.
3.What payment methods are accepted for X9250US24Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X9250US24Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X9250US24Z?
X9250US24Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X9250US24Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X9250US24Z?
For technical support, including X9250US24Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X9250US24Z requirements.
6.How does Aetrix verify that X9250US24Z is sourced from the original manufacturer or authorized distributors?
All X9250US24Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X9250US24Z meets industry standards.
7.What is the process for return or replacement of X9250US24Z?
All X9250US24Z units undergo pre-shipment inspection (PSI). If there is an issue with X9250US24Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X9250US24Z part is unused and in its original packaging.
Return procedure for X9250US24Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X9250US24Z Tags

-
MCP4018T-103E/LT
Microchip Technology

-
MCP4018T-503E/LT
Microchip Technology

-
MCP4011T-103E/SN
Microchip Technology

-
MCP4018T-104E/LT
Microchip Technology

-
MCP4017T-503E/LT
Microchip Technology

-
MCP4018T-502E/LT
Microchip Technology

-
MCP4017T-103E/LT
Microchip Technology

-
MCP4531T-103E/MF
Microchip Technology

-
MCP4021T-202E/SN
Microchip Technology

-
MCP4023T-103E/CH
Microchip Technology

-
MCP4022T-503E/CH
Microchip Technology

-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

