Renesas X9250UV24
- Part No.:
- X9250UV24
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
X9250UV24.pdf
- Description:
- IC DGT POT 50KOHM 256TAP 24TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,498
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X9250UV24 from Intersil is a quad digitally controlled potentiometer (XDCP™) with 256-tap resolution per channel, SPI serial interface, dual analog supply support (±2.7V to ±5.5V), and nonvolatile wiper position storage. It operates over -40°C to +85°C in a 24-lead TSSOP package and delivers 40Ω typical wiper resistance at 5V, enabling precision analog control in mixed-signal systems.
For engineers reviewing the X9250UV24 datasheet, X9250UV24 pinout, X9250UV24 application, or X9250UV24 equivalent, this device serves as a drop-in replacement for mechanical potentiometers in programmable gain stages, offset calibration circuits, and multi-channel sensor conditioning where digital reconfiguration, long-term setting retention, and low-power standby (<5µA) are required.
Technical Context
The X9250UV24 integrates four independent 255-segment resistor arrays with CMOS switch-controlled wipers, each driven by an 8-bit volatile Wiper Counter Register (WCR) and backed by four 8-bit nonvolatile Data Registers (DR0–DR3). Its SPI interface supports full-duplex communication with rising-edge data latching on SI and falling-edge data output on SO, and includes hardware write protection (WP) and HOLD for serial bus arbitration.
It supports true dual-supply operation: V+ and V− independently set analog rail limits (±2.7V to ±5.5V), while VCC powers the digital core (2.7V–5.5V). Power-up automatically loads DR0 into each WCR, and nonvolatile writes complete in ≤10ms with internal high-voltage programming circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total resistance | 100kΩ per potentiometer - sets maximum voltage division range and current handling (50mW rating per pot) |
| Resolution | 256 taps (0.4% step size) - enables fine-grained analog adjustment with <1mV error in 5V full-scale applications |
| Wiper resistance | 40Ω typical at VCC = 5V - minimizes signal path distortion in precision attenuator or gain-setting configurations |
| Supply range | VCC = 2.7V–5.5V; V+ = +2.7V–+5.5V; V− = −2.7V–−5.5V - supports bipolar signal conditioning without level-shifting circuitry |
| Standby current | <5µA total package - enables always-on calibration memory in battery-powered instrumentation |
| Data retention | 100 years - ensures factory-trimmed offsets or user-configured settings persist across product lifetime |
| Endurance | 100,000 write cycles per register - supports frequent recalibration in automated test equipment without wear-out risk |
Pinout & Package
Package: 24-lead TSSOP (4.4mm body width, MDP0044 footprint), RoHS-compliant Pb-free plus anneal finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: S0 | Serial Output | Tri-state SPI data output; clocks out read data on SCK falling edge - enables daisy-chaining or shared bus with other SPI peripherals |
| 2: A0 | Device Address LSB | Configures slave address bit A0; allows up to four X9250UV24 devices on one SPI bus without software address translation |
| 3: VW3/RW3 | Potentiometer 3 wiper | Active analog output node for Pot 3; connects internally to one of 256 resistor taps - used for variable gain or offset injection |
| 4: V+ | Analog positive supply | Positive rail for all four potentiometer arrays; must be ≥|V−| and ≤12V differential from V− - defines upper signal swing limit |
| 5: VCC | Digital supply | Powers SPI interface, control logic, and WCR registers; independent of V+/V− - allows digital domain to operate at 3.3V while analog rails run at ±5V |
| 6: VL0/RL0 | Pot 0 low terminal | Fixed end of Pot 0 resistor array; tied to V− or system ground depending on configuration - sets lower reference for voltage divider |
| 7–10: HOLD, SCK, VL2/RL2, VH2/RH2 | Bus control & Pot 2 terminals | HOLD pauses ongoing SPI transfers; SCK clocks data; VL2/VH2 define Pot 2's analog endpoints - enables synchronous multi-pot updates |
| 11–14: V−, VSS, VW1/RW1, VH1/RH1 | Analog negative supply, ground, Pot 1 wiper & high terminal | V− sets negative analog rail; VSS is digital ground; VW1 provides adjustable output from Pot 1 - critical for bipolar op-amp biasing |
| 15–18: VL1/RL1, VH3/RH3, VL3/RL3, VH0/RH0 | Pot 1/3/0 low/high terminals | Complete terminal access for all four pots - supports independent three-terminal pot or two-terminal rheostat use per channel |
| 19–24: CS, A1, SI, WP, VW0/RW0, NC | Chip select, address MSB, serial input, write protect, Pot 0 wiper, no-connect | CS enables SPI interface; A1 completes 2-bit address; SI accepts opcodes/data; WP disables NV writes; VW0 is Pot 0 output; NC unused |
Key Features
| Feature | Design Value |
|---|---|
| Four independent 256-tap XDCPs | Enables simultaneous calibration of four signal paths (e.g., multi-channel ADC front-end gain/offset) without external multiplexing |
| SPI-compatible serial interface | Reduces MCU GPIO count vs. parallel control; supports up to 4 devices on one bus using A0/A1 addressing - simplifies BOM in space-constrained designs |
| Nonvolatile wiper storage (DR0–DR3) | Preserves last-set values across power cycles - eliminates boot-time reinitialization in medical sensors or industrial controllers |
| Dual analog supply (V+/V−) | Supports true bipolar operation (±2.7V to ±5.5V) - allows direct interfacing with op-amps, comparators, or DACs requiring symmetric rails |
| Hardware write protection (WP) | Prevents accidental overwriting of calibrated settings during firmware updates or field service - enhances system reliability in deployed equipment |
| Low standby current (<5µA) | Permits continuous memory retention in energy-harvesting or battery-backed systems without compromising runtime - critical for portable test gear |
Applications
| Instrumentation Offset Calibration | Programmable Gain Amplifier |
|---|---|
|
Use Scenario: Precision nulling of DC offset in multi-channel data acquisition front-ends before ADC sampling. IC Role / Device Role / Timing Role: X9250UV24 acts as four independent 100kΩ digital potentiometers, each injecting calibrated counter-voltage into op-amp summing junctions. Use Value: Achieves <±100µV offset correction across temperature (-40°C to +85°C) with 100-year nonvolatile retention - eliminates manual trimmer adjustments and drift-related recalibration. |
Use Scenario: Dynamic gain selection in ultrasound receiver chains where signal amplitude varies widely between tissue types. IC Role / Device Role / Timing Role: X9250UV24 configures feedback resistors in noninverting amplifier topology; SPI updates occur synchronously between echo bursts. Use Value: Enables 12dB–48dB gain steps with <0.1% resistor matching error and <10µs wiper response - maintains signal integrity during real-time beamforming. |
| Bipolar Voltage Regulator Trim | Multi-Channel Sensor Linearization |
|
Use Scenario: Fine-tuning output voltage of dual-rail ±12V switching regulators in FPGA power supplies. IC Role / Device Role / Timing Role: X9250UV24 replaces mechanical trimpots on TL317/TL337 regulator feedback dividers, with separate pots for +VOUT and −VOUT loops. Use Value: Supports remote, firmware-controlled regulation within ±0.5% accuracy over line/load/temperature - eliminates field service visits for voltage drift correction. |
Use Scenario: Compensating nonlinearity in four thermistor-based temperature sensors across automotive cabin zones. IC Role / Device Role / Timing Role: X9250UV24 implements piecewise-linear correction by adjusting individual op-amp bias points in analog signal paths prior to digitization. Use Value: Delivers ±0.25°C measurement accuracy from −40°C to +125°C using factory-stored DR values - meets ASIL-B functional safety requirements without software overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ100 | Single 256-tap 100kΩ pot; I²C interface; no dual-supply analog rails | Limited to unipolar operation (0–5V); lacks independent V+/V− support for bipolar signal paths | Select when only one channel is needed and system uses I²C; avoid for bipolar op-amp biasing or multi-channel trimming |
| MCP42050-I/SL | Dual 256-tap 50kΩ pots; SPI interface; single 2.7–5.5V supply; no nonvolatile storage | Requires external EEPROM for setting retention; wiper position lost on power loss | Choose for cost-sensitive, single-supply designs where recalibration at boot is acceptable; not suitable for fail-safe calibration memory |
Compared with AD5242BRUZ100 and MCP42050-I/SL, the X9250UV24 uniquely combines quad-channel integration, true bipolar analog supply capability (V+/V−), and guaranteed 100-year nonvolatile storage - making it the only option for space-constrained, safety-critical, or maintenance-free multi-rail analog systems.
Availability
X9250UV24 is available at Aetrix Electronics and suitable for instrumentation offset calibration, programmable gain amplifiers, bipolar voltage regulator trim, and multi-channel sensor linearization requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for X9250UV24 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil (now part of Renesas Electronics) is a semiconductor manufacturer specializing in precision analog, power management, and interface ICs for industrial, aerospace, and communications markets.
The X9250UV24 belongs to Intersil's XDCP™ family of digitally controlled potentiometers, designed specifically for replacing mechanical trimmers in high-reliability analog signal conditioning where programmability, nonvolatility, and multi-channel integration are essential.
FAQ
What is the operating temperature range for the X9250UV24?
The X9250UV24 is rated for industrial operation from −40°C to +85°C. This range is confirmed in the Ordering Information table (X9250UV24I variant) and applies to all electrical specifications including wiper resistance, resolution, and nonvolatile write timing. The device maintains full functionality across this range without derating.
Does the X9250UV24 support true bipolar analog operation?
Yes, the X9250UV24 supports true bipolar analog operation via dedicated V+ and V− pins, rated from ±2.7V to ±5.5V. Each of the four potentiometer arrays references these rails independently, enabling direct connection to op-amps or comparators requiring symmetric analog supplies - a capability not found in most single-supply digital potentiometers.
How many nonvolatile data registers does the X9250UV24 provide per potentiometer?
The X9250UV24 provides four 8-bit nonvolatile Data Registers (DR0–DR3) for each of its four potentiometers. These registers store wiper positions or system parameters and retain data for 100 years. DR0 is automatically loaded into the Wiper Counter Register at power-up, providing deterministic startup behavior.
What is the maximum SPI clock frequency supported by the X9250UV24?
The X9250UV24 supports a maximum SPI clock frequency of 2.0 MHz, as specified in the AC Timing section. This allows full 16-bit instruction sequences (e.g., Write Data Register) to complete in under 8µs, enabling rapid reconfiguration of all four potentiometers in real-time control loops.
Can the X9250UV24 be used as a two-terminal variable resistor?
Yes, the X9250UV24 can be configured as a two-terminal variable resistor by connecting either VH/RH or VL/RL to the wiper (VW/RW) terminal, leaving the other fixed terminal open or grounded. This configuration is explicitly supported in the Applications Information section and maintains the same 256-step resolution and nonvolatile storage.
X9250UV24 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 4
- Number of Taps:
- 256
- Resistance (Ohms):
- 50k
- Interface:
- SPI
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- ±5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±300ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-TSSOP
- Operating Temperature:
- 0°C ~ 70°C
- Resistance - Wiper (Ohms) (Typ):
- 150
X9250UV24 FAQ
1.How can I place an order for X9250UV24 through Aetrix?
Please submit a Request for Quotation (RFQ) for X9250UV24 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X9250UV24 reliable?
The price and inventory of X9250UV24 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X9250UV24 is usually 5 days.
3.What payment methods are accepted for X9250UV24?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X9250UV24 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X9250UV24?
X9250UV24 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X9250UV24 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X9250UV24?
For technical support, including X9250UV24 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X9250UV24 requirements.
6.How does Aetrix verify that X9250UV24 is sourced from the original manufacturer or authorized distributors?
All X9250UV24 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X9250UV24 meets industry standards.
7.What is the process for return or replacement of X9250UV24?
All X9250UV24 units undergo pre-shipment inspection (PSI). If there is an issue with X9250UV24, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X9250UV24 part is unused and in its original packaging.
Return procedure for X9250UV24:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X9250UV24 Tags

-
MCP4018T-103E/LT
Microchip Technology

-
MCP4018T-503E/LT
Microchip Technology

-
MCP4011T-103E/SN
Microchip Technology

-
MCP4018T-104E/LT
Microchip Technology

-
MCP4017T-503E/LT
Microchip Technology

-
MCP4018T-502E/LT
Microchip Technology

-
MCP4017T-103E/LT
Microchip Technology

-
MCP4531T-103E/MF
Microchip Technology

-
MCP4021T-202E/SN
Microchip Technology

-
MCP4023T-103E/CH
Microchip Technology

-
MCP4022T-503E/CH
Microchip Technology

-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

