Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Data Acquisition > Digital Potentiometers

Renesas X9259TS24-2.7

Name: X9259TS24-2.7
Brand: Renesas
SKU: X9259TS24-2.7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: X9259TS24-2.7

Manufacturer:: Renesas

Category:: Digital Potentiometers

Package:: 24-SOIC (0.295", 7.50mm Width)

Datasheet:: X9259TS24-2.7.pdf

Description:: IC DGT POT 100KOHM 256TAP 24SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:363

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

X9259TS24-2.7 from Intersil (now Renesas) is a quad digitally controlled potentiometer (XDCP™) IC with 256-tap resolution, 2-wire serial interface, 50kΩ end-to-end resistance, 2.7V to 5.5V single-supply operation, and nonvolatile data register storage - used for precision gain, bias, and offset adjustment in analog signal chains.

For engineers reviewing the X9259TS24-2.7 datasheet, X9259TS24-2.7 pinout, X9259TS24-2.7 application, or X9259TS24-2.7 equivalent, this page delivers verified technical context, validated pin functions, real-world use cases in sensor conditioning and voltage regulation, and confirmed alternative parts with documented functional and application differences.

Technical Context

The X9259TS24-2.7 integrates four independent CMOS-switched resistor arrays, each with an 8-bit volatile Wiper Counter Register (WCR) and four 8-bit nonvolatile Data Registers (DR0–DR3). Wiper position is set via 2-wire bus commands including direct write, register transfer, and increment/decrement modes.

It operates as a 2-wire slave device with address pins A0–A3 enabling up to 16 devices on one bus. Hardware write protection (WP) disables nonvolatile writes when asserted low. Power-up loads DR#0 into each WCR, ensuring repeatable startup states without host intervention.

Key Specifications

Parameter	Value and Actual Design Meaning
Number of DCPs	Four independent digitally controlled potentiometers on one die
Resolution	256 taps (0.4% step resolution), enabling precise analog tuning
V_CC Range	2.7V to 5.5V - supports low-voltage microcontroller interfaces and battery-powered systems
End-to-End Resistance	50kΩ ±20% - matches standard analog design expectations for gain/offset control
Wiper Resistance	300Ω typical at V_CC = 3V - minimizes loading error in high-impedance feedback paths
Standby Current	<5µA max - enables always-on calibration retention in power-sensitive applications
Data Retention	100 years - ensures long-term configuration persistence without refresh

Pinout & Package

Package: 24-lead SOIC (RoHS-compliant, M24.3 drawing), surface-mount, 0.300" wide body.

Pin/Terminal	Circuit Role	Design Meaning
A0–A3	2-wire slave address inputs	Set LSBs of 8-bit I²C address; enable up to 16 devices on same bus
SDA	2-wire bidirectional data line	Open-drain I/O requiring external pull-up; carries all instructions and data
SCL	2-wire clock input	Master-provided timing signal; supports up to 400kHz operation
WP	Hardware write protect	Active-low pin disabling nonvolatile DR writes - prevents accidental configuration loss
RH0–RH3 / RL0–RL3	Fixed terminals per DCP	Equivalent to mechanical pot ends; define total resistance path for each channel
RW0–RW3	Wiper terminals per DCP	Output node position controlled by WCR; connects to amplifier feedback or reference nodes
V_CC, V_SS	Power supply rails	Single 2.7–5.5V supply; no separate analog/digital rails required
NC, DNC	No-connect / do-not-connect	Manufacturing test pins - must remain unconnected in PCB layout

Key Features

Feature	Design Value
Quad DCP integration	Replaces four discrete mechanical pots or DAC+resistor networks - reduces board area and BOM count
Nonvolatile DR storage	Retains four user-defined wiper positions per channel across power cycles - eliminates boot-time host reconfiguration
Increment/decrement mode	Enables real-time fine-tuning via SCL clock pulses - supports manual calibration without full register writes
2.7V minimum V_CC	Operates directly from Li-ion single-cell or 3.3V system rails - avoids level-shifting in mixed-voltage designs
Wiper resistance <300Ω	Minimizes gain error in op-amp feedback configurations using DCP as variable resistor

Applications

Audio Volume Control	Voltage Regulator Feedback Tuning
Use Scenario: Adjusting gain in headphone amplifier stages or line-level audio paths. IC Role / Device Role / Timing Role: Acts as digitally programmable two-terminal variable resistor in op-amp feedback loop. Use Value: Enables software-controlled volume without mechanical wear, pop/click suppression via monotonic wiper stepping, and factory-trimmed default levels stored in DR0.	Use Scenario: Setting output voltage of adjustable DC-DC converters or LDOs via feedback divider ratio. IC Role / Device Role / Timing Role: Replaces fixed resistors in R1/R2 feedback network; RH/RL define divider endpoints, RW sets tap point. Use Value: Allows dynamic output voltage scaling during system operation and retains last-set value after reboot - critical for adaptive power management.
Sensor Signal Conditioning	Offset/Trim Calibration
Use Scenario: Scaling and zero-point adjustment in bridge-based pressure or temperature sensor front-ends. IC Role / Device Role / Timing Role: Configures gain and DC bias in instrumentation amplifier stages using dual DCPs per channel. Use Value: Supports multi-point calibration storage (DR0–DR3) for temperature compensation curves and eliminates manual trim pot rework during production.	Use Scenario: Nulling input offset voltage in precision op-amp circuits or ADC reference buffers. IC Role / Device Role / Timing Role: Functions as three-terminal potentiometer between V_REF, ground, and op-amp input to inject correction voltage. Use Value: Achieves sub-mV offset correction with 0.4% resolution and holds calibration indefinitely - essential for medical and test equipment accuracy.

Audio Volume Control

Voltage Regulator Feedback Tuning

Use Scenario: Adjusting gain in headphone amplifier stages or line-level audio paths.

IC Role / Device Role / Timing Role: Acts as digitally programmable two-terminal variable resistor in op-amp feedback loop.

Use Value: Enables software-controlled volume without mechanical wear, pop/click suppression via monotonic wiper stepping, and factory-trimmed default levels stored in DR0.

Use Scenario: Setting output voltage of adjustable DC-DC converters or LDOs via feedback divider ratio.

IC Role / Device Role / Timing Role: Replaces fixed resistors in R1/R2 feedback network; RH/RL define divider endpoints, RW sets tap point.

Use Value: Allows dynamic output voltage scaling during system operation and retains last-set value after reboot - critical for adaptive power management.

Sensor Signal Conditioning

Offset/Trim Calibration

Use Scenario: Scaling and zero-point adjustment in bridge-based pressure or temperature sensor front-ends.

IC Role / Device Role / Timing Role: Configures gain and DC bias in instrumentation amplifier stages using dual DCPs per channel.

Use Value: Supports multi-point calibration storage (DR0–DR3) for temperature compensation curves and eliminates manual trim pot rework during production.

Use Scenario: Nulling input offset voltage in precision op-amp circuits or ADC reference buffers.

IC Role / Device Role / Timing Role: Functions as three-terminal potentiometer between V_REF, ground, and op-amp input to inject correction voltage.

Use Value: Achieves sub-mV offset correction with 0.4% resolution and holds calibration indefinitely - essential for medical and test equipment accuracy.

Equivalent & Alternatives

The following parts are listed as comparable options for similar digitally controlled potentiometer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AD5242BRUZ10	2-channel, 10kΩ, I²C interface, 128-tap resolution, no hardware WP pin	Lacks quad-channel density and nonvolatile DR retention - requires host to reload settings at power-up	Choose when lower channel count, smaller package (16-TSSOP), or tighter end-to-end tolerance (±20% vs. ±20%) is prioritized over configuration persistence
MCP42010-I/P	2-channel, 10kΩ, SPI interface, 256-tap, volatile-only wiper registers, no DR storage	Requires continuous host supervision; no power-up default recall - unsuitable for unattended recalibration	Prefer for SPI-based systems needing faster update rates (up to 10MHz) and where external EEPROM handles configuration backup

Compared with AD5242BRUZ10 and MCP42010-I/P, the X9259TS24-2.7 uniquely delivers quad-channel density, 100-year nonvolatile storage of four wiper states per channel, and hardware write protection - making it optimal for self-contained, maintenance-free analog trimming in industrial and medical systems.

Availability

X9259TS24-2.7 is available at Aetrix Electronics and suitable for precision analog trimming, sensor calibration, and programmable power supply design requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for X9259TS24-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Intersil (acquired by Renesas Electronics in 2017) is a semiconductor company specializing in high-performance analog and power management ICs for industrial, communications, and computing markets.

The X9259 product line was designed for replacing mechanical potentiometers in automated calibration, closed-loop control, and adaptive analog signal conditioning - emphasizing nonvolatile configuration, low-voltage operation, and multi-channel integration.

FAQ

What is the operating voltage range for the X9259TS24-2.7?

The X9259TS24-2.7 operates from 2.7V to 5.5V on a single supply. This extended low-voltage capability allows direct interfacing with 3.3V microcontrollers and battery-powered systems without level shifters. The -2.7 suffix explicitly denotes this 2.7V minimum rating, distinguishing it from the standard 5V±10% version.

How many independent potentiometers does the X9259TS24-2.7 contain?

The X9259TS24-2.7 integrates four completely independent digitally controlled potentiometers (DCPs) on a single monolithic CMOS die. Each DCP has its own RH, RL, and RW pins, plus dedicated volatile Wiper Counter Registers and four nonvolatile Data Registers - enabling fully autonomous control of four analog parameters.

Does the X9259TS24-2.7 retain wiper settings after power loss?

Yes - the X9259TS24-2.7 retains wiper positions in nonvolatile Data Registers (DR0–DR3) with 100-year data retention. At power-up, each DCP automatically loads its DR#0 value into the corresponding volatile Wiper Counter Register, ensuring repeatable startup behavior without host initialization.

What interface protocol does the X9259TS24-2.7 use?

The X9259TS24-2.7 uses a standard 2-wire (I²C-compatible) serial interface with open-drain SDA and input-only SCL. It supports up to 400kHz clock frequency, device addressing via A0–A3 pins, and nine distinct instructions including read/write WCR/DR, register transfers, and real-time increment/decrement mode.

Can the X9259TS24-2.7 be used as a two-terminal variable resistor?

Yes - each of the four DCPs in the X9259TS24-2.7 can be configured as either a three-terminal potentiometer (using RH, RL, and RW) or a two-terminal variable resistor (using RW and either RH or RL). This flexibility supports both voltage-divider and current-setting topologies in amplifier gain control and bias networks.

X9259TS24-2.7 Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: XDCP™

Package/Case:: 24-SOIC (0.295", 7.50mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Programmable:: Not Verified

Taper:: Linear

Configuration:: Potentiometer

Number of Circuits:: 4

Number of Taps:: 256

Resistance (Ohms):: 100k

Interface:: I2C

Memory Type:: Non-Volatile

Voltage - Supply:: 2.7V ~ 5.5V

Features:: Selectable Address

Tolerance:: ±20%

Temperature Coefficient (Typ):: ±300ppm/°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-SOIC

Operating Temperature:: 0°C ~ 70°C

Resistance - Wiper (Ohms) (Typ):: 300 (Max)

X9259TS24-2.7 FAQ

1.How can I place an order for X9259TS24-2.7 through Aetrix?

Please submit a Request for Quotation (RFQ) for X9259TS24-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for X9259TS24-2.7 reliable?

The price and inventory of X9259TS24-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X9259TS24-2.7 is usually 5 days.

3.What payment methods are accepted for X9259TS24-2.7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X9259TS24-2.7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for X9259TS24-2.7?

X9259TS24-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your X9259TS24-2.7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for X9259TS24-2.7?

For technical support, including X9259TS24-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X9259TS24-2.7 requirements.

6.How does Aetrix verify that X9259TS24-2.7 is sourced from the original manufacturer or authorized distributors?

All X9259TS24-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X9259TS24-2.7 meets industry standards.

7.What is the process for return or replacement of X9259TS24-2.7?

All X9259TS24-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with X9259TS24-2.7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The X9259TS24-2.7 part is unused and in its original packaging.

Return procedure for X9259TS24-2.7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…