Renesas X9313UST2
- Part No.:
- X9313UST2
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
X9313UST2.pdf
- Description:
- IC DGTL POT 50KOHM 32TAP 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,631
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X9313UST2 from Intersil is a digitally controlled potentiometer (XDCP™) implementing a 32-tap linear resistor array with nonvolatile wiper position storage, 3-wire serial interface (CS/U/D/INC), ±VCC terminal voltage tolerance, and 10 kΩ end-to-end resistance - used for precision analog trimming in voltage reference and op-amp feedback networks.
For engineers reviewing the X9313UST2 datasheet, X9313UST2 pinout, X9313UST2 application, or X9313UST2 equivalent, key selection criteria include wiper endurance (100,000 cycles), power-up recall behavior, ±4.4 mA max wiper current, and compatibility with 3–5.5 V supply rails in industrial temperature range (−40°C to +85°C).
Technical Context
The X9313UST2 integrates a 31-element resistor ladder, 5-bit up/down counter, make-before-break wiper switching, and EEPROM-based nonvolatile memory for wiper position retention. Its control logic responds to edge-triggered INC input synchronized with U/D direction and CS enable, enabling deterministic tap stepping without microcontroller polling.
Operation supports both three-terminal potentiometer (VH–VW–VL) and two-terminal variable resistor configurations. Wiper resistance is 40 Ω typical at VCC = 5 V, and terminal voltage range spans −VCC to +VCC, allowing bipolar signal conditioning in op-amp circuits.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| End-to-end resistance (RTOTAL) | 10 kΩ ±20% - sets gain/attenuation scale in feedback or divider networks |
| Wiper positions | 32 discrete taps (0–31) - provides 3.125% resolution per step across full range |
| Supply voltage (VCC) | 3 V to 5.5 V - compatible with mixed-signal systems using 3.3 V or 5 V rails |
| Wiper current limit | ±4.4 mA - defines max load current before nonlinear wiper resistance dominates |
| Nonvolatile storage | 100-year data retention, 100,000 write cycles - enables field calibration without battery backup |
| Terminal voltage range | −VCC to +VCC - supports AC-coupled or dual-supply analog signal paths |
| Operating temperature | −40°C to +85°C - qualified for industrial-grade embedded control environments |
Pinout & Package
Package: 8-lead SOIC (Pb-free, RoHS compliant), 3.9 mm × 4.9 mm body, 1.27 mm pitch - surface-mount compatible with standard reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Positive supply rail | Power source for internal logic and resistor array; must be stable before CS activation |
| VSS | Ground reference | Common return for logic and analog terminals; requires low-impedance connection |
| RH/VH | High terminal | Fixed end of resistor array; voltage may exceed VCC or go negative within −VCC to +VCC limits |
| RL/VL | Low terminal | Fixed opposite end; polarity relative to RH/VH depends on U/D state, not voltage potential |
| RW/VW | Wiper output | Movable tap point; series resistance ~40 Ω at 5 V - affects loading in high-impedance nodes |
| CS | Chip select | Active-low enable; HIGH with INC HIGH triggers nonvolatile store; LOW enables U/D/INC control |
| U/D | Direction control | Defines increment/decrement direction during INC transitions; may change dynamically while CS is LOW |
| INC | Increment clock | Negative-edge triggered; each pulse moves wiper one tap; timing min 2 µs cycle, 1 µs HIGH/LOW |
Key Features
| Feature | Design Value |
|---|---|
| Solid-state construction | Eliminates mechanical wear, contact bounce, and vibration sensitivity vs. rotary pots |
| 3-wire serial interface | Requires only three GPIOs (CS/U/D/INC) - no SPI/I²C peripheral needed |
| Power-up recall | Automatically restores last stored wiper position at VCC ramp completion (tPU = 10 µs) |
| Make-before-break switching | Prevents open-circuit glitches during tap transitions - critical for stable feedback loops |
| Temperature-compensated array | ±300 ppm/°C end-to-end drift - maintains ratio accuracy across industrial temperature range |
Applications
| Reference Voltage Trimming | Op-Amp Gain Adjustment |
|---|---|
Use Scenario: Fine-tuning output of a bandgap reference IC (e.g., REF5025) to meet ±0.1% initial accuracy spec under varying PCB thermal gradients. IC Role / Device Role / Timing Role: Two-terminal variable resistor in the reference divider network; wiper position set once at factory and recalled on every power cycle. Use Value: Replaces manual laser trimming; achieves repeatability <±0.05% over 100,000 cycles and 100-year data retention. | Use Scenario: Dynamically adjusting closed-loop gain of an instrumentation amplifier (e.g., INA128) in response to sensor signal amplitude changes. IC Role / Device Role / Timing Role: Three-terminal potentiometer in noninverting amplifier feedback path; wiper updated via microcontroller during runtime. Use Value: Enables software-controlled gain ranging (e.g., 1× to 1000×) without external relays or analog switches. |
| Comparator Hysteresis Setting | Power Supply Feedback Divider |
Use Scenario: Configuring upper/lower thresholds in a TL072-based window comparator for motor overcurrent detection. IC Role / Device Role / Timing Role: Dual-ratio divider using RH–VW and VW–RL segments to set VUL and VLL; values stored in NV memory for consistent trip points. Use Value: Eliminates mismatch from discrete resistor pairs; ensures hysteresis width remains stable across temperature (±20 ppm/°C ratiometric TC). | Use Scenario: Adjusting output voltage of an LM317 adjustable regulator in a programmable bench power supply. IC Role / Device Role / Timing Role: Three-terminal potentiometer replacing mechanical trimmer in ADJ pin feedback network; wiper position saved after user calibration. Use Value: Enables digital front-panel control of output voltage with persistent setting across AC power cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5243BRMZ10 | I²C interface, dual-channel, 256-tap resolution, 10 kΩ RAB, ±20% tolerance | Requires I²C master; higher resolution but no native power-up recall (requires external controller initialization) | Select when multi-channel trimming or finer adjustment granularity is required and I²C infrastructure exists |
| MCP41010-I/P | Single-channel SPI interface, 256-tap, 10 kΩ, volatile wiper register (no NV memory) | Needs external MCU to reload wiper value on power-up; lacks autonomous recall capability | Select when cost-sensitive designs accept firmware-dependent initialization and do not require factory-set persistence |
Compared with AD5243BRMZ10 and MCP41010-I/P, the X9313UST2 uniquely delivers autonomous power-up recall, 3-wire minimal GPIO footprint, and bipolar terminal voltage support - making it optimal for industrial systems where reliability, simplicity, and analog signal integrity are prioritized over communication protocol flexibility.
Availability
X9313UST2 is available at Aetrix Electronics and suitable for industrial sensor calibration, programmable power supplies, and analog front-end trimming requiring stable component supply, long-term obsolescence management, and RoHS-compliant packaging.
Supply support for X9313UST2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a precision analog and power management semiconductor provider, now part of Renesas Electronics, with deep expertise in high-reliability industrial and infrastructure solutions.
The X9313 product line was designed specifically for solid-state replacement of mechanical potentiometers in analog signal conditioning, offering nonvolatile storage, temperature-stable resistance ratios, and robust ESD performance for harsh operating environments.
FAQ
What is the maximum allowable voltage difference between VH and VL terminals for the X9313UST2?
The X9313UST2 specifies ΔV = |VH − VL| ≤ 10 V for the X9313W/X9313U family variants. Since X9313UST2 is an X9313U variant (per ordering table: "X9313USZ" and "X9313USIZ" denote U-series, 10 kΩ, industrial temp), its absolute maximum terminal differential is 10 V. Exceeding this risks irreversible damage to the internal resistor array or switching transistors.
Does the X9313UST2 require an external pull-up resistor on the INC pin?
No, the X9313UST2 does not require an external pull-up on the INC pin. Its INC input has CMOS-compatible thresholds (VIL ≤ 0.8 V, VIH ≥ 2 V) and leakage current ≤ ±10 µA, allowing direct connection to microcontroller GPIOs configured as push-pull outputs. Internal pull-ups are not provided, but external ones are unnecessary unless open-drain driving is used.
How is the wiper position stored in nonvolatile memory on the X9313UST2?
The X9313UST2 stores the current wiper position when CS transitions HIGH while INC is held HIGH. This store operation takes 10 ms (tWR). During that time, the device enters standby mode and ignores further INC pulses. Once complete, the value persists for 100 years and is automatically loaded into the wiper counter on next power-up, independent of external control.
Can the X9313UST2 be used in a bipolar signal path where VH is at −2.5 V and VL is at +2.5 V?
Yes - the X9313UST2 supports terminal voltages from −VCC to +VCC. With VCC = 5 V, VH and VL may each range from −5 V to +5 V, so −2.5 V and +2.5 V are fully within specification. The wiper (VW) will track proportionally between them, and the 10 kΩ RTOTAL remains valid across this range, enabling true bipolar AC signal attenuation.
What is the typical wiper resistance of the X9313UST2 and how does it affect circuit performance?
The X9313UST2 has a typical wiper resistance (RW) of 40 Ω at VCC = 5 V, with a maximum of 100 Ω. In high-gain op-amp feedback networks or low-impedance divider applications, this series resistance introduces gain error and temperature-dependent offset. For example, in a 10 kΩ total pot, 40 Ω adds ~0.4% error - acceptable for most trimming tasks but must be modeled in precision references.
X9313UST2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 1
- Number of Taps:
- 32
- Resistance (Ohms):
- 50k
- Interface:
- Up/Down (U/D, INC, CS)
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 5V
- Features:
- -
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±300ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 8-SOIC
- Operating Temperature:
- 0°C ~ 70°C
- Resistance - Wiper (Ohms) (Typ):
- 40
X9313UST2 FAQ
1.How can I place an order for X9313UST2 through Aetrix?
Please submit a Request for Quotation (RFQ) for X9313UST2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X9313UST2 reliable?
The price and inventory of X9313UST2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X9313UST2 is usually 5 days.
3.What payment methods are accepted for X9313UST2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X9313UST2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X9313UST2?
X9313UST2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X9313UST2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X9313UST2?
For technical support, including X9313UST2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X9313UST2 requirements.
6.How does Aetrix verify that X9313UST2 is sourced from the original manufacturer or authorized distributors?
All X9313UST2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X9313UST2 meets industry standards.
7.What is the process for return or replacement of X9313UST2?
All X9313UST2 units undergo pre-shipment inspection (PSI). If there is an issue with X9313UST2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X9313UST2 part is unused and in its original packaging.
Return procedure for X9313UST2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X9313UST2 Tags

-
MCP4018T-103E/LT
Microchip Technology

-
MCP4018T-503E/LT
Microchip Technology

-
MCP4011T-103E/SN
Microchip Technology

-
MCP4018T-104E/LT
Microchip Technology

-
MCP4017T-503E/LT
Microchip Technology

-
MCP4018T-502E/LT
Microchip Technology

-
MCP4017T-103E/LT
Microchip Technology

-
MCP4531T-103E/MF
Microchip Technology

-
MCP4021T-202E/SN
Microchip Technology

-
MCP4023T-103E/CH
Microchip Technology

-
MCP4022T-503E/CH
Microchip Technology

-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

