Renesas X9313WSMT2
- Part No.:
- X9313WSMT2
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
X9313WSMT2.pdf
- Description:
- IC DGTL POT 10KOHM 32TAP 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,812
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X9313WSMT2 from Intersil is a digitally controlled potentiometer (XDCP™) implementing a 32-tap linear resistor array with nonvolatile wiper position storage, 3-wire serial interface (CS/U/D/INC), ±VCC terminal voltage range, and 10kΩ end-to-end resistance - used for precision analog trimming in voltage reference and op-amp feedback networks.
For engineers reviewing the X9313WSMT2 datasheet, X9313WSMT2 pinout, X9313WSMT2 application, or X9313WSMT2 equivalent, key selection criteria include its 10kΩ RTOTAL tolerance (±20%), wiper resistance (40Ω typ at 5V), 3V–5.5V supply compatibility, -40°C to +85°C industrial temperature range, and MSOP-8 package footprint.
Technical Context
The X9313WSMT2 integrates a 31-element resistor ladder, 5-bit up/down counter, nonvolatile memory for power-up recall, and make-before-break wiper switching. Its control logic responds to negative-edge-triggered INC pulses while U/D sets direction, and CS enables operation or initiates nonvolatile store on high-going edge with INC high.
It operates as either a three-terminal potentiometer (RH/VH–RW/VW–RL/VL) or two-terminal variable resistor, with terminal voltages rated from –VCC to +VCC and absolute linearity error limited to ±1 MI (minimum increment = RTOTAL/31).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RTOTAL | 10kΩ ±20% - defines full-scale resistance for gain/offset calibration accuracy |
| Wiper Resolution | 32 taps (31 steps) - provides 3.125% per-step adjustment granularity |
| VCC Range | 3V to 5.5V - supports dual-supply systems and legacy 5V rails |
| Terminal Voltage Range | –VCC to +VCC - enables bipolar signal handling without external level-shifting |
| Wiper Resistance | 40Ω typical at VCC = 5V - limits loading error in high-impedance feedback paths |
| Nonvolatile Endurance | 100,000 wiper position changes - ensures long-term field reliability in recalibration loops |
| Data Retention | 100 years - maintains factory or user-set trim values across product lifetime |
Pinout & Package
Package: 8-lead MSOP (Moisture Sensitivity Level 1, Pb-free, RoHS compliant, JEDEC MO-187-AA compliant, 3.0mm × 3.0mm body, 0.65mm pitch).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Positive supply input | Power rail for internal logic and resistor array; must be stabilized before CS activation |
| VSS | Ground reference | Common return for all digital and analog functions; requires low-impedance connection |
| RH/VH | High terminal | Fixed end of resistor array; voltage polarity relative to wiper depends on U/D state |
| RL/VL | Low terminal | Fixed end of resistor array; forms voltage divider with RH/VH and RW/VW |
| RW/VW | Wiper output | Movable tap point; series resistance ≤100Ω affects precision in current-sensing applications |
| CS | Chip select | Active-low enable; rising edge with INC high triggers nonvolatile store of current wiper position |
| U/D | Direction control | Logic level sets wiper movement direction during subsequent INC transitions |
| INC | Increment clock | Negative-edge-triggered; toggles wiper position one step per pulse, subject to U/D state |
Key Features
| Feature | Design Value |
|---|---|
| Nonvolatile wiper storage | Retains last-set position across power cycles - eliminates boot-time reinitialization in embedded systems |
| 3-wire serial interface | Requires only CS, U/D, and INC signals - minimizes GPIO usage vs. I²C/SPI alternatives |
| Make-before-break switching | Prevents open-circuit transients during wiper movement - avoids glitches in active filter or amplifier feedback paths |
| Temperature-compensated array | ±300 ppm/°C RTOTAL drift - maintains calibration stability over industrial temperature range |
| Bipolar terminal rating | Supports –VCC to +VCC voltage swing - enables direct use in AC-coupled or dual-supply signal chains |
Applications
| Reference Voltage Trimming | Op-Amp Gain Calibration |
|---|---|
Use Scenario: Adjusting output voltage of an LM317-based adjustable regulator via R1/R2 feedback network. IC Role / Device Role / Timing Role: Two-terminal variable resistor replacing R2 to set precise VOUT = 1.25V × (1 + R2/R1). Use Value: Enables factory or field calibration without soldering; 10kΩ RTOTAL matches typical LM317 design ranges and limits current draw to <125µA at 1.25V. | Use Scenario: Setting closed-loop gain of TL072 noninverting amplifier in test equipment front-end. IC Role / Device Role / Timing Role: Three-terminal potentiometer in R2 feedback path (VH→R2→VW→op-amp input; VL grounded). Use Value: Provides 32-step digital gain adjustment (e.g., 1× to 10×) with <0.5% step resolution and no mechanical wear. |
| Comparator Hysteresis Control | Audio Tone Control |
Use Scenario: Configuring upper/lower trip thresholds (VUL/VLL) in LT311A comparator with hysteresis. IC Role / Device Role / Timing Role: Two-terminal resistor forming R1 in voltage divider (R1/(R1+R2)) that sets hysteresis width. Use Value: Allows dynamic hysteresis tuning to suppress noise-induced oscillation; ±VCC rating accommodates ±12V comparator supplies. | Use Scenario: Implementing bass/treble tone stack in analog audio preamplifier using passive RC network. IC Role / Device Role / Timing Role: Three-terminal potentiometer replacing mechanical tone pot, with VH/VL as input/output and VW as wiper feed to filter node. Use Value: Eliminates scratch noise and contact degradation; 10kΩ value matches standard audio impedance levels and minimizes capacitive loading. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5243BRMZ10 | I²C interface, dual-channel, 256-tap resolution, 10kΩ RTOTAL, ±30% tolerance | Requires I²C bus and microcontroller firmware support; higher resolution but looser resistance tolerance | Preferred when multi-channel trimming or finer adjustment granularity is required |
| MCP41010-I/P | SPI interface, single-channel, 257-tap resolution, 10kΩ RTOTAL, ±20% tolerance, volatile wiper register | No nonvolatile storage - wiper resets to mid-scale on power-up; needs external EEPROM or host initialization | Chosen where SPI is already present and power-cycle retention is not mandatory |
Compared with X9313WSMT2, AD5243BRMZ10 offers higher resolution and dual-channel capability but lacks guaranteed ±20% RTOTAL tolerance and requires I²C infrastructure; MCP41010-I/P provides SPI compatibility and identical RTOTAL tolerance but forfeits automatic power-up recall, demanding host-side wiper restoration logic.
Availability
X9313WSMT2 is available at Aetrix Electronics and suitable for voltage reference trimming, op-amp gain calibration, and comparator hysteresis control requiring stable component supply across industrial temperature ranges and long product lifecycles.
Supply support for X9313WSMT2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation is a precision analog and power management semiconductor company, now part of Renesas Electronics, with expertise in high-reliability industrial and infrastructure solutions.
The X9313 family was designed for solid-state replacement of mechanical potentiometers in analog signal conditioning, offering nonvolatile setting retention and digital interface simplicity for embedded calibration tasks.
FAQ
What is the supply voltage range supported by the X9313WSMT2?
The X9313WSMT2 operates from 3V to 5.5V DC. This range allows compatibility with both modern low-voltage systems and legacy 5V designs. The device's internal CMOS circuitry draws ≤3mA active current and ≤500µA standby current within this range, ensuring minimal power impact in battery-powered or thermally constrained applications. The X9313WSMT2 datasheet specifies performance parameters under these conditions, including wiper resistance and timing characteristics.
Does the X9313WSMT2 retain its wiper position after power loss?
Yes, the X9313WSMT2 stores the wiper position in nonvolatile memory and automatically recalls it on power-up. This occurs without external intervention - the stored value is loaded into the wiper counter within 10µs after VCC stabilizes. The memory endurance is rated for 100,000 write cycles, and data retention exceeds 100 years at +25°C. This behavior makes the X9313WSMT2 ideal for applications requiring repeatable startup states, such as factory-calibrated instruments or safety-critical bias settings.
What package type is used for the X9313WSMT2?
The X9313WSMT2 uses an 8-lead MSOP (Mini Small Outline Package) with 0.65mm lead pitch, 3.0mm × 3.0mm body dimensions, and Pb-free RoHS-compliant finish. It conforms to JEDEC MO-187-AA standards and has Moisture Sensitivity Level 1. The package supports standard reflow soldering profiles and is compatible with automated pick-and-place assembly. Pin 1 is marked by a notch or dot, and the pinout matches the standard X9313 MSOP configuration shown in the FN8177 datasheet.
Can the X9313WSMT2 be used with bipolar analog signals?
Yes, the X9313WSMT2 supports terminal voltages from –VCC to +VCC, enabling direct use with bipolar signals such as ±5V or ±12V. This allows implementation in AC-coupled circuits, dual-supply op-amps, and comparators without external level-shifting components. The resistor array remains functional across this full range, and the wiper maintains make-before-break operation regardless of signal polarity. Absolute maximum ratings specify ±6V on VH/VL/VW terminals relative to VSS, consistent with industrial signal chain requirements.
How does the 3-wire interface of the X9313WSMT2 differ from I²C or SPI protocols?
The X9313WSMT2 uses a proprietary 3-wire interface (CS, U/D, INC) rather than standardized protocols like I²C or SPI. It requires no address decoding, clock stretching, or ACK/NACK handshaking - wiper movement is controlled by simple edge-triggered INC pulses synchronized with U/D direction and CS enable. This reduces firmware overhead and GPIO count versus bus-based alternatives. Unlike I²C/SPI DCPs, the X9313WSMT2 does not support readback of wiper position or status registers, focusing solely on robust, low-complexity write-only trimming.
X9313WSMT2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 1
- Number of Taps:
- 32
- Resistance (Ohms):
- 10k
- Interface:
- Up/Down (U/D, INC, CS)
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 5V
- Features:
- -
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±300ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 8-SOIC
- Operating Temperature:
- 0°C ~ 70°C
- Resistance - Wiper (Ohms) (Typ):
- 40
X9313WSMT2 FAQ
1.How can I place an order for X9313WSMT2 through Aetrix?
Please submit a Request for Quotation (RFQ) for X9313WSMT2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X9313WSMT2 reliable?
The price and inventory of X9313WSMT2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X9313WSMT2 is usually 5 days.
3.What payment methods are accepted for X9313WSMT2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X9313WSMT2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X9313WSMT2?
X9313WSMT2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X9313WSMT2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X9313WSMT2?
For technical support, including X9313WSMT2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X9313WSMT2 requirements.
6.How does Aetrix verify that X9313WSMT2 is sourced from the original manufacturer or authorized distributors?
All X9313WSMT2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X9313WSMT2 meets industry standards.
7.What is the process for return or replacement of X9313WSMT2?
All X9313WSMT2 units undergo pre-shipment inspection (PSI). If there is an issue with X9313WSMT2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X9313WSMT2 part is unused and in its original packaging.
Return procedure for X9313WSMT2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X9313WSMT2 Tags

-
MCP4018T-103E/LT
Microchip Technology

-
MCP4018T-503E/LT
Microchip Technology

-
MCP4011T-103E/SN
Microchip Technology

-
MCP4018T-104E/LT
Microchip Technology

-
MCP4017T-503E/LT
Microchip Technology

-
MCP4018T-502E/LT
Microchip Technology

-
MCP4017T-103E/LT
Microchip Technology

-
MCP4531T-103E/MF
Microchip Technology

-
MCP4021T-202E/SN
Microchip Technology

-
MCP4023T-103E/CH
Microchip Technology

-
MCP4022T-503E/CH
Microchip Technology

-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

