Renesas X9455UV24-2.7
- Part No.:
- X9455UV24-2.7
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
X9455UV24-2.7.pdf
- Description:
- IC DGT POT 50KOHM 256TAP 24TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
X9455UV24-2.7 from Intersil is a dual two-wiper digitally controlled potentiometer (XDCP™) with 256-tap resolution per wiper, 50 kΩ end-to-end resistance, and operation from 2.7V to 5.5V. It integrates two independent resistor arrays-each with dual wipers-and supports both 2-wire serial and Up/Down interfaces for volatile/non-volatile wiper control. Used in precision bias voltage programming and programmable gain networks.
For engineers reviewing the X9455UV24-2.7 datasheet, X9455UV24-2.7 pinout, X9455UV24-2.7 application, or X9455UV24-2.7 equivalent, this page delivers verified specifications, validated pin functions, confirmed dual-DCP architecture, non-volatile wiper storage behavior, and real-world interface timing constraints for embedded trimming and calibration systems.
Technical Context
The X9455UV24-2.7 implements two monolithic CMOS resistor arrays, each with 255 segments and four dedicated wiper terminals (RW0A/RW0B/RW1A/RW1B), enabling true four-terminal potentiometer operation. Each array uses an 8-bit volatile Wiper Counter Register (WCR) decoded to select one of 256 tap points, with four non-volatile Data Registers (DR0A0–DR1B3) per wiper.
It supports concurrent dual-interface operation: 2-wire (SCL/SDA, up to 400 kHz) for register-level access and Up/Down (CS/U/D/DS0/DS1) for direct wiper stepping. Power-on recall loads DR0A0/DR0B0/DR1A0/DR1B0 into respective WCRs, and hardware write protection (WP) disables non-volatile writes when asserted low.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total resistance | 50 kΩ - defines full-scale voltage division range and load interaction in bias networks. |
| Resolution | 0.4% - corresponds to 256 discrete tap positions, enabling ±1 LSB accuracy in trim applications. |
| Wiper resistance | 40 Ω typical - limits insertion error and signal attenuation in high-impedance feedback paths. |
| Supply voltage | 2.7 V to 5.5 V - ensures compatibility with 3.3 V and 5 V logic domains without level shifting. |
| Standby current | < 20 µA max - enables battery-powered calibration circuits with minimal quiescent drain. |
| Non-volatile endurance | 100,000 data changes per bit - supports field recalibration over product lifetime without wear-out risk. |
| Data retention | 100 years - guarantees wiper position persistence across decades of storage or infrequent power cycles. |
| Interface speed | 400 kHz 2-wire clock - allows sub-millisecond register updates for dynamic gain adjustment. |
Pinout & Package
Package: 24-lead TSSOP (4.4 mm wide), RoHS-compliant Pb-free plus anneal option available.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RL0, RH0, RW0A, RW0B | DCP0 low/high/wiper A/wiper B terminals | Enable four-terminal configuration for DCP0: RL0/RH0 define voltage span; RW0A/RW0B provide independent output taps. |
| RL1, RH1, RW1A, RW1B | DCP1 low/high/wiper A/wiper B terminals | Enable independent four-terminal operation for DCP1-supports dual-channel trimming without cross-coupling. |
| SCL, SDA, A0–A2, CS, WP | 2-wire and Up/Down control inputs | SCL/SDA enable register read/write; A0–A2 set slave address; CS selects Up/Down mode; WP gates non-volatile writes. |
| U/D, DS0, DS1, VCC, VSS | Wiper direction, DCP selection, supply | U/D sets increment/decrement; DS0/DS1 select wiper (00→W0A, 11→W0B, 10→W1A, 01→W1B); VCC/VSS power core logic and resistor arrays. |
Key Features
| Feature | Design Value |
|---|---|
| Dual two-wiper architecture | Two independent 256-tap resistor arrays, each with two physically separate wipers-enables simultaneous dual-ratio or differential output generation. |
| Volatile + non-volatile wiper storage | Each wiper has one volatile WCR and four non-volatile DRs; power-up loads DRxY0 into WCR, ensuring repeatable startup state without host initialization. |
| Hardware write protection | WP pin disables all non-volatile writes (2-wire "Write DR" and Up/Down "Store") when pulled low-prevents accidental EEPROM corruption during system debug or noise events. |
| 2-wire + Up/Down dual interface | Full register access via 2-wire; fast manual stepping via U/D/SCL/CS-supports both automated calibration (microcontroller-driven) and user-adjustable trims (front-panel encoder). |
| Low wiper resistance | 40 Ω typical - minimizes voltage error in high-gain op-amp feedback loops where wiper current flows through feedback path. |
| End-to-end resistance matching | 0.75–2.0% between DCP0 and DCP1 - ensures matched gain scaling in dual-path signal conditioning (e.g., stereo audio, differential ADC reference). |
Applications
| Programmable Bias Voltage Generator | Window Comparator Threshold Setter |
|---|---|
|
Use Scenario: Setting precise upper/lower thresholds in a dual-comparator window detector for overvoltage/undervoltage monitoring. IC Role / Device Role / Timing Role: X9455UV24-2.7 provides independently adjustable RH/RL-referenced voltage dividers for each comparator input, using RW0A and RW1A as threshold outputs. Use Value: Eliminates manual trimming pots; enables factory calibration and field recalibration via microcontroller-reducing BOM count and improving long-term stability vs. mechanical pots. |
Use Scenario: Configuring offset and gain in a programmable instrumentation amplifier front-end for sensor signal conditioning. IC Role / Device Role / Timing Role: X9455UV24-2.7 acts as dual-ratio divider: DCP0 sets gain (feedback ratio), DCP1 sets offset (reference injection point). Use Value: Achieves <±0.4% linearity error across temperature; non-volatile storage preserves calibrated offsets after power loss-critical for medical or industrial sensors. |
| Three-Resistor Programmable Network | Dual-Channel LED Current Limiter |
|
Use Scenario: Implementing a three-terminal programmable resistor network for active filter tuning (e.g., Sallen-Key topology). IC Role / Device Role / Timing Role: X9455UV24-2.7 configures RH0–RW0A–RW0B–RL0 as a variable series-shunt network, with RW0A/RW0B defining intermediate node voltages. Use Value: Enables digital reconfiguration of cutoff frequency without component swaps; 50 kΩ total resistance matches standard op-amp drive capability and noise performance. |
Use Scenario: Controlling brightness of two independent LED strings in display backlighting or automotive lighting modules. IC Role / Device Role / Timing Role: X9455UV24-2.7 serves as dual current-setting pot: DCP0 adjusts LED1 current via RW0A–RL0; DCP1 adjusts LED2 via RW1A–RL1. Use Value: Supports 3 mA max wiper current per terminal-sufficient for direct LED biasing at 20 mA total; standby current <20 µA extends battery life in portable designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5242BRUZ10 | Single 256-tap DCP, 10 kΩ, I²C interface only, no Up/Down pins. | Lacks dual-DCP and dual-wiper capability; cannot replicate four-terminal or independent dual-channel operation of X9455UV24-2.7. | Select when only single-channel trimming is needed and board space is constrained-requires redesign for dual-path use cases. |
| MCP42050-I/SL | Dual 257-tap DCP, 50 kΩ, SPI interface, no non-volatile storage. | No EEPROM; wiper positions reset on power cycle-requires host MCU to reload values at boot. | Choose for cost-sensitive, high-volume applications where calibration is performed at final test and retained externally. |
Compared with AD5242BRUZ10 and MCP42050-I/SL, the X9455UV24-2.7 uniquely delivers dual two-wiper architecture with non-volatile storage and dual-interface support-making it irreplaceable for applications requiring independent, persistent, four-terminal trimming without host intervention.
Availability
X9455UV24-2.7 is available at Aetrix Electronics and suitable for precision analog trimming, sensor calibration, and programmable power supply feedback networks requiring stable component supply and long-term parameter retention.
Supply support for X9455UV24-2.7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil (now part of Renesas Electronics) is a semiconductor company specializing in high-performance analog and mixed-signal ICs for power management, precision analog, and interface applications.
The X9455UV24-2.7 belongs to Intersil's XDCP™ family of digitally controlled potentiometers, designed specifically for replacing mechanical trimmers in industrial, medical, and communications equipment where reliability, repeatability, and programmability are critical.
FAQ
What is the total end-to-end resistance of the X9455UV24-2.7?
The X9455UV24-2.7 has a nominal end-to-end resistance of 50 kΩ, as specified in the Ordering Information table on page 2 of FN8202 Rev 1.00. This value applies to both DCP0 and DCP1 arrays and is guaranteed within ±20% tolerance across temperature and voltage. The 50 kΩ version is explicitly designated by the "U" in the part number X9455UV24-2.7.
Does the X9455UV24-2.7 retain wiper settings after power cycling?
Yes, the X9455UV24-2.7 retains wiper positions in non-volatile memory. On power-up, the contents of DR0A0, DR0B0, DR1A0, and DR1B0 are automatically loaded into their corresponding Wiper Counter Registers (WCR0A, WCR0B, WCR1A, WCR1B). Data retention is rated for 100 years, and endurance is 100,000 write cycles per bit.
Can the X9455UV24-2.7 operate from a 3.3 V supply?
Yes, the X9455UV24-2.7 operates from 2.7 V to 5.5 V, fully supporting standard 3.3 V logic and supply rails. All DC electrical specifications-including ICC1 (3 mA max), ISB (<20 µA), and VIH/VIL thresholds-are validated across this range. The "-2.7" suffix confirms minimum operating voltage compliance.
How many wiper terminals does the X9455UV24-2.7 provide?
The X9455UV24-2.7 provides four wiper terminals: RW0A and RW0B for DCP0, and RW1A and RW1B for DCP1. Each wiper connects to its own 8-bit volatile Wiper Counter Register and associated non-volatile Data Registers, enabling true dual two-wiper functionality per array.
What interfaces does the X9455UV24-2.7 support for wiper control?
The X9455UV24-2.7 supports two independent interfaces: a 2-wire (I²C-compatible) interface using SCL/SDA/A0–A2/CS/WP, and an Up/Down interface using CS/U/D/DS0/DS1. Both interfaces can configure wiper positions, but only the 2-wire interface allows full register-level access to all Data Registers and Status Register.
X9455UV24-2.7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 2
- Number of Taps:
- 256
- Resistance (Ohms):
- 50k
- Interface:
- I2C, Up/Down (U/D, CS)
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 2.7V ~ 5.5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±300ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-TSSOP
- Operating Temperature:
- 0°C ~ 70°C
- Resistance - Wiper (Ohms) (Typ):
- 50
X9455UV24-2.7 FAQ
1.How can I place an order for X9455UV24-2.7 through Aetrix?
Please submit a Request for Quotation (RFQ) for X9455UV24-2.7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X9455UV24-2.7 reliable?
The price and inventory of X9455UV24-2.7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X9455UV24-2.7 is usually 5 days.
3.What payment methods are accepted for X9455UV24-2.7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X9455UV24-2.7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X9455UV24-2.7?
X9455UV24-2.7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X9455UV24-2.7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X9455UV24-2.7?
For technical support, including X9455UV24-2.7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X9455UV24-2.7 requirements.
6.How does Aetrix verify that X9455UV24-2.7 is sourced from the original manufacturer or authorized distributors?
All X9455UV24-2.7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X9455UV24-2.7 meets industry standards.
7.What is the process for return or replacement of X9455UV24-2.7?
All X9455UV24-2.7 units undergo pre-shipment inspection (PSI). If there is an issue with X9455UV24-2.7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X9455UV24-2.7 part is unused and in its original packaging.
Return procedure for X9455UV24-2.7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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