Renesas X95840UV20I-2.7T1
- Part No.:
- X95840UV20I-2.7T1
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
X95840UV20I-2.7T1.pdf
- Description:
- IC DGT POT 50KOHM 256TAP 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,675
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Product details
Overview
X95840UV20I-2.7T1 from Intersil is a quad digital controlled potentiometer (XDCP™) IC with 50kΩ total resistance per channel, 256-tap I²C interface, non-volatile initial value registers, and 20-lead TSSOP packaging. It operates from 2.7V to 5.5V, delivers <5µA standby current, and serves as precision voltage divider or rheostat in analog signal conditioning circuits.
For engineers reviewing the X95840UV20I-2.7T1 datasheet, X95840UV20I-2.7T1 pinout, X95840UV20I-2.7T1 application, or X95840UV20I-2.7T1 equivalent, key selection criteria include I²C address configurability (A0–A2), hardware write protection (WP), wiper resistance (70Ω typ), DCP-to-DCP matching (±2 LSB), and industrial temperature range (−40°C to +85°C).
Technical Context
The X95840UV20I-2.7T1 integrates four independent digitally controlled potentiometers on a monolithic CMOS die, each with volatile Wiper Register (WR) and non-volatile Initial Value Register (IVR). Wiper position is set via 8-bit register values (0x00–0xFF), enabling monotonic 0.4% resolution adjustment between RH and RL terminals.
It implements I²C slave protocol with 400kHz max clock frequency, supports up to eight devices per bus via A0–A2 address pins, and features hardware write protection (WP active-low). Power-up recalls IVR contents into WRs, and non-volatile writes require explicit STOP condition initiation with tWP = 12–20ms internal cycle time.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 50kΩ per DCP - sets full-scale voltage division ratio and maximum rheostat resistance. |
| Resolution | 256 taps (8-bit) - enables 0.4% step resolution for fine analog control. |
| Wiper Resistance | 70Ω typical at 3.3V - limits insertion error and signal attenuation in voltage divider mode. |
| Supply Range | 2.7V to 5.5V - compatible with 3.3V and 5V logic/system rails without level shifting. |
| Standby Current | <5µA at 5.5V - enables low-power operation in battery-backed or energy-sensitive systems. |
| I²C Clock Max | 400kHz - supports standard-mode I²C timing without requiring high-speed peripherals. |
| Temperature Range | −40°C to +85°C - qualified for industrial-grade embedded analog control applications. |
Pinout & Package
Package: 20-lead Thin Shrink Small Outline Package (TSSOP), RoHS-compliant, Pb-free plus anneal finish, body dimensions 6.5mm × 4.4mm × 1.2mm (D × E1 × A2).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RH3, RH2, RH1, RH0 | High terminal of DCP3–DCP0 | Fixed end of resistor string; connects to VCC or reference voltage in voltage divider mode. |
| RL3, RL2, RL1, RL0 | Low terminal of DCP3–DCP0 | Fixed end of resistor string; connects to GND or signal return in voltage divider mode. |
| RW3, RW2, RW1, RW0 | Wiper terminal of DCP3–DCP0 | Adjustable tap point; output node for voltage division or variable resistance path. |
| SDA, SCL | I²C bidirectional data/clock | Standard open-drain interface; requires external pull-ups (1–20kΩ depending on bus capacitance). |
| A0, A1, A2 | I²C device address inputs | Three binary address bits - configure one of eight possible I²C addresses (0xA0–0xA7). |
| WP | Hardware write protect input | Active-low; disables all I²C writes when pulled low, preventing accidental register corruption. |
| VCC, GND | Power supply and ground | Single 2.7–5.5V supply; decoupling capacitor recommended near VCC pin. |
Key Features
| Feature | Design Value |
|---|---|
| Quad DCP integration | Four independent 50kΩ potentiometers in single 20-pin TSSOP - reduces board space vs discrete solutions and ensures matched performance. |
| Non-volatile IVR storage | 50-year data retention at ≤75°C - preserves factory or user-defined startup wiper positions across power cycles without external EEPROM. |
| Hardware write protection | WP pin prevents unintended I²C writes - critical for field-deployed systems where firmware updates or noise could corrupt settings. |
| DCP-to-DCP matching | ±2 LSB wiper voltage matching across all four channels - enables precise multi-channel gain/offset calibration in instrumentation amplifiers. |
| Low-power standby | <5µA ICC at 5.5V - allows continuous I²C bus presence while minimizing quiescent load in always-on sensor interfaces. |
Applications
| Audio Volume Control | Programmable Gain Amplifier |
|---|---|
Use Scenario: Digital volume adjustment in professional audio mixers with mute/solo functionality and recallable presets. IC Role / Device Role / Timing Role: Quad DCP acts as four independent voltage dividers setting analog signal attenuation before ADC or post-DAC reconstruction. Use Value: Eliminates mechanical pot wear, enables remote calibration via I²C, and retains last-set volume after power loss using non-volatile IVRs. | Use Scenario: Gain configuration in multi-channel medical ECG front-end amplifiers requiring matched channel response. IC Role / Device Role / Timing Role: Each DCP configures feedback resistance in op-amp transimpedance stages, adjusting sensitivity per electrode channel. Use Value: ±2 LSB DCP matching ensures ≤0.3% inter-channel gain mismatch, meeting IEC 60601-2-27 common-mode rejection requirements. |
| Industrial Sensor Calibration | Power Supply Trim |
Use Scenario: Field-adjustable offset/zero trim for 4–20mA loop-powered pressure transmitters during commissioning. IC Role / Device Role / Timing Role: Two DCPs serve as precision rheostats in DAC output buffer networks to calibrate zero and span outputs. Use Value: 70Ω wiper resistance minimizes trim error contribution; 150,000-cycle endurance supports repeated recalibration over product lifetime. | Use Scenario: Factory-trimmed output voltage adjustment for isolated DC-DC converters in telecom power modules. IC Role / Device Role / Timing Role: One DCP replaces mechanical trimpot in feedback divider network of secondary-side TL431-based regulation loop. Use Value: Non-volatile IVR stores final trim value; I²C interface enables automated test system programming during manufacturing, reducing manual labor. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5204BRUZ10 | Quad 10kΩ DCP, SPI interface, no hardware WP pin, 30ppm/°C TCR | Lacks I²C compatibility and write protection; higher tempco affects precision voltage division stability | Select when SPI host interface exists and WP not required; verify 10kΩ matches circuit impedance needs. |
| MCP41010-I/P | Single 10kΩ DCP, SPI interface, 10-bit resolution, no non-volatile storage | Requires four separate packages for quad function; volatile-only storage mandates external memory for power-up state | Choose for cost-sensitive single-channel use; avoid for multi-channel matched applications or state retention requirements. |
Compared with AD5204BRUZ10 and MCP41010-I/P, the X95840UV20I-2.7T1 provides native I²C support with hardware write protection and guaranteed 50kΩ resistance-critical for industrial voltage divider designs requiring bus efficiency, tamper resistance, and fixed impedance scaling.
Availability
X95840UV20I-2.7T1 is available at Aetrix Electronics and suitable for industrial sensor calibration, programmable gain amplifier design, and power supply trimming requiring stable component supply, long-term lifecycle continuity, and RoHS-compliant packaging.
Supply support for X95840UV20I-2.7T1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) designs high-performance analog and mixed-signal ICs for industrial, communications, and computing markets, with ISO 9001-certified manufacturing.
The X95840 family targets digitally reconfigurable analog signal conditioning, delivering quad-channel precision potentiometer functionality with non-volatile state retention and industrial-grade reliability.
FAQ
What is the total resistance value specified for the X95840UV20I-2.7T1?
The X95840UV20I-2.7T1 is the 50kΩ variant of the X95840 family, confirmed by its "U" suffix in the part marking (X95840UV G) and datasheet ordering table. Each of its four DCPs has a nominal end-to-end resistance of 50kΩ, with ±20% tolerance across temperature and voltage conditions.
Does the X95840UV20I-2.7T1 retain wiper settings after power cycling?
Yes - the X95840UV20I-2.7T1 automatically loads wiper positions from its non-volatile Initial Value Registers (IVRs) at power-up. These IVRs retain data for 50 years at ≤75°C, ensuring repeatable startup behavior without external memory or host initialization.
How many I²C addresses can be assigned to the X95840UV20I-2.7T1?
The X95840UV20I-2.7T1 supports eight unique I²C addresses (0xA0–0xA7) via three hardware address pins (A0, A1, A2). This allows up to eight devices on a single I²C bus without address conflict, simplifying multi-channel system design.
What is the purpose of the WP pin on the X95840UV20I-2.7T1?
The WP (Write Protect) pin on the X95840UV20I-2.7T1 is an active-low hardware lock that disables all I²C write operations when asserted. This prevents accidental register modification due to noise, software bugs, or unauthorized access - essential for field-deployed equipment integrity.
Can the X95840UV20I-2.7T1 operate from a 3.3V supply?
Yes - the X95840UV20I-2.7T1 is fully specified for operation from 2.7V to 5.5V, including standard 3.3V systems. Its wiper resistance (70Ω typ), I²C timing (400kHz), and leakage specs (≤1µA on DCP pins) are all validated at 3.3V and 25°C per the datasheet.
X95840UV20I-2.7T1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 4
- Number of Taps:
- 256
- Resistance (Ohms):
- 50k
- Interface:
- I2C
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 2.7V ~ 5.5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±45ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-TSSOP
- Operating Temperature:
- -40°C ~ 85°C
- Resistance - Wiper (Ohms) (Typ):
- 70
X95840UV20I-2.7T1 FAQ
1.How can I place an order for X95840UV20I-2.7T1 through Aetrix?
Please submit a Request for Quotation (RFQ) for X95840UV20I-2.7T1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X95840UV20I-2.7T1 reliable?
The price and inventory of X95840UV20I-2.7T1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X95840UV20I-2.7T1 is usually 5 days.
3.What payment methods are accepted for X95840UV20I-2.7T1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X95840UV20I-2.7T1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X95840UV20I-2.7T1?
X95840UV20I-2.7T1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X95840UV20I-2.7T1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X95840UV20I-2.7T1?
For technical support, including X95840UV20I-2.7T1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X95840UV20I-2.7T1 requirements.
6.How does Aetrix verify that X95840UV20I-2.7T1 is sourced from the original manufacturer or authorized distributors?
All X95840UV20I-2.7T1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X95840UV20I-2.7T1 meets industry standards.
7.What is the process for return or replacement of X95840UV20I-2.7T1?
All X95840UV20I-2.7T1 units undergo pre-shipment inspection (PSI). If there is an issue with X95840UV20I-2.7T1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X95840UV20I-2.7T1 part is unused and in its original packaging.
Return procedure for X95840UV20I-2.7T1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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