Renesas X95840UV20IZ-2.7T1
- Part No.:
- X95840UV20IZ-2.7T1
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
X95840UV20IZ-2.7T1.pdf
- Description:
- IC DGT POT 50KOHM 256TAP 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,421
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
X95840UV20IZ-2.7T1 from Intersil is a quad digital controlled potentiometer (XDCP™) IC with 50kΩ total resistance per channel, 256-tap I²C interface, non-volatile initial value registers, and 20-lead TSSOP packaging. It operates from 2.7V to 5.5V, delivers <5µA standby current, and serves as precision programmable resistors in analog signal conditioning circuits for industrial sensor interfaces and audio level control.
For engineers reviewing the X95840UV20IZ-2.7T1 datasheet, X95840UV20IZ-2.7T1 pinout, X95840UV20IZ-2.7T1 application, or X95840UV20IZ-2.7T1 equivalent, key selection criteria include I²C address configurability (A0–A2), hardware write protection (WP), wiper resistance (70Ω typ), and guaranteed monotonicity in both voltage divider and rheostat modes across –40°C to +85°C.
Technical Context
The X95840UV20IZ-2.7T1 integrates four independent digitally controlled potentiometers on a monolithic CMOS die, each with volatile Wiper Registers (WR) and non-volatile Initial Value Registers (IVR). Its I²C slave interface supports up to eight devices per bus via A0–A2 address pins and includes hardware write protection via active-low WP.
Each DCP implements resistor ladders with CMOS switches; wiper position is set by an 8-bit WR (0x00–0xFF), enabling 0.4% resolution. At power-up, IVR contents load into WRs, and the device defaults to mid-scale (0x80) until recalled - ensuring repeatable startup behavior without host intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Total Resistance | 50kΩ per DCP - defines full-scale analog range in voltage divider or rheostat configurations |
| Resolution | 256 taps (8-bit) - enables 0.4% step resolution for fine-grained analog tuning |
| Wiper Resistance | 70Ω typical at 3.3V - limits insertion error and signal attenuation in low-impedance paths |
| Supply Range | 2.7V to 5.5V - supports single-supply operation across 3.3V and 5V systems |
| Standby Current | <5µA max at 5.5V - enables ultra-low-power retention in battery-backed or always-on systems |
| I²C Speed | 400kHz - compatible with standard-mode Fast-mode I²C controllers without timing margin risk |
| Non-volatile Endurance | 150,000 write cycles - supports field calibration and long-term configuration storage |
Pinout & Package
Package: 20-lead TSSOP (Thin Shrink Small Outline Package), RoHS-compliant Pb-free plus anneal finish, 6.5mm × 4.4mm body, 0.65mm pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RH3, RH2, RH1, RH0 | High terminal of DCP3–DCP0 | Fixed end of resistor ladder; connects to VCC or reference voltage in voltage divider mode |
| RL3, RL2, RL1, RL0 | Low terminal of DCP3–DCP0 | Fixed end of resistor ladder; connects to GND or signal return in voltage divider mode |
| RW3, RW2, RW1, RW0 | Wiper terminal of DCP3–DCP0 | Programmable tap point; output node for variable voltage or resistance in analog signal paths |
| SDA, SCL | I²C bidirectional data/clock | Standard open-drain interface requiring external pull-ups; supports multi-master arbitration |
| A0, A1, A2 | I²C device address inputs | Three binary inputs enabling up to eight unique addresses (0x50–0x57) on shared bus |
| WP | Hardware write protect | Active-low pin preventing accidental writes to volatile/non-volatile registers during operation |
| VCC, GND | Power supply and ground | Single 2.7–5.5V supply; decoupling capacitor required within 10mm of VCC/GND pins |
Key Features
| Feature | Design Value |
|---|---|
| Quad DCP integration | Four independent 50kΩ potentiometers in one 20-pin TSSOP - reduces board space vs discrete solutions and ensures matched temperature drift |
| Non-volatile IVR storage | Retains startup wiper positions across power cycles without external EEPROM - eliminates boot-time host initialization overhead |
| Monotonic performance | DNL ≤ ±0.5 LSB in both voltage divider and rheostat modes - guarantees no code-to-code glitches in closed-loop control |
| Ratiometric tempco | ±4 ppm/°C - maintains stable voltage division ratio over temperature, critical for precision sensor biasing |
| Hardware write protection | Active-low WP pin prevents register corruption during ESD events or firmware faults - enhances system reliability in harsh environments |
Applications
| Industrial Sensor Calibration | Audio Signal Level Control |
|---|---|
Use Scenario: Adjusting gain/offset of 4–20mA transmitter front-end circuits in process automation systems. IC Role / Device Role / Timing Role: Four-channel programmable resistor network setting bias points and feedback ratios for op-amp-based transducer signal conditioning. Use Value: Enables field recalibration via I²C without hardware modification; 50kΩ range matches common industrial loop impedance requirements. | Use Scenario: Digital volume control in professional audio mixers with analog signal path preservation. IC Role / Device Role / Timing Role: Quad DCP acting as four independent attenuators in line-level signal chains, driven by microcontroller I²C commands. Use Value: Eliminates mechanical pot wear and channel mismatch; 256-step resolution provides smooth, repeatable level adjustment. |
| Programmable Power Supply Trim | Medical Instrument Gain Setting |
Use Scenario: Fine-tuning output voltage of isolated DC-DC converters in telecom power modules. IC Role / Device Role / Timing Role: Voltage divider configuration feeding feedback node of secondary-side error amplifier; wiper position sets regulation setpoint. Use Value: Allows post-manufacturing calibration and dynamic output adjustment; non-volatile IVR retains trim value after power loss. | Use Scenario: Configuring gain of biopotential amplifier stages (ECG/EEG) to match varying electrode impedances. IC Role / Device Role / Timing Role: Rheostat-mode DCP in op-amp feedback path to set programmable gain without switching noise or contact bounce. Use Value: 70Ω wiper resistance minimizes gain error; monotonic DNL ensures no signal distortion during real-time gain changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5204BRUZ10 | Quad 10kΩ DCP, SPI interface, 128-tap resolution, 35Ω wiper resistance | Lacks I²C compatibility and non-volatile IVR; requires SPI host and external memory for persistent settings | Select when SPI-native host architecture exists and lower wiper resistance is prioritized over I²C simplicity |
| MCP42050-I/SL | Quad 50kΩ DCP, SPI interface, 256-tap resolution, 120Ω wiper resistance, no hardware WP pin | Higher wiper resistance increases insertion loss; lacks dedicated write-protect pin, increasing firmware dependency for register safety | Choose when existing SPI infrastructure dominates and board layout constraints favor SOIC-14 over TSSOP-20 |
Compared with AD5204BRUZ10 and MCP42050-I/SL, the X95840UV20IZ-2.7T1 offers native I²C support with configurable addressing, integrated hardware write protection, and guaranteed monotonicity - reducing firmware complexity and improving robustness in multi-device analog control systems.
Availability
X95840UV20IZ-2.7T1 is available at Aetrix Electronics and suitable for industrial sensor calibration, audio signal level control, programmable power supply trim, and medical instrument gain setting requiring stable component supply and long-term lifecycle continuity.
Supply support for X95840UV20IZ-2.7T1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Intersil Corporation (now part of Renesas Electronics) designs high-performance analog and mixed-signal ICs for power management, precision analog, and interface applications.
The X95840 product line delivers digitally programmable analog components targeting systems needing field-calibratable, non-volatile, and I²C-configurable resistance networks - especially in industrial, medical, and test equipment where repeatability and reliability are critical.
FAQ
What is the total resistance and resolution of the X95840UV20IZ-2.7T1?
The X95840UV20IZ-2.7T1 features four independent 50kΩ digital potentiometers, each with 256 linearly spaced taps (8-bit resolution), delivering 0.4% step resolution. This allows precise analog tuning in voltage divider or rheostat configurations without external scaling components. The resistance tolerance is ±20%, and ratiometric temperature coefficient is ±4 ppm/°C - ensuring stable division ratios across temperature.
Does the X95840UV20IZ-2.7T1 retain wiper settings after power cycling?
Yes, the X95840UV20IZ-2.7T1 retains wiper startup values using non-volatile Initial Value Registers (IVRs). At power-up, the device automatically loads the stored IVR values into the volatile Wiper Registers (WRs), ensuring repeatable behavior without host intervention. Each IVR supports 150,000 write cycles and 50-year data retention at ≤75°C - meeting long-life industrial deployment requirements.
How does the WP pin function on the X95840UV20IZ-2.7T1?
The WP (Write Protect) pin on the X95840UV20IZ-2.7T1 is an active-low hardware lock that disables all I²C write operations when pulled LOW. When WP is HIGH, normal read/write access to volatile and non-volatile registers is enabled. This feature prevents accidental register corruption during firmware updates, ESD events, or brown-out conditions - enhancing system reliability in mission-critical analog control paths.
Can multiple X95840UV20IZ-2.7T1 devices share the same I²C bus?
Yes, up to eight X95840UV20IZ-2.7T1 devices can operate on a single I²C bus using the A0, A1, and A2 address pins to configure unique 7-bit slave addresses (0x50–0x57). Each device responds only to its assigned address, enabling coordinated control of 32 independent DCP channels from one microcontroller - ideal for multi-channel instrumentation or modular analog signal processing systems.
What is the maximum wiper current rating for the X95840UV20IZ-2.7T1?
The X95840UV20IZ-2.7T1 specifies a maximum wiper current of ±3.0mA per DCP channel under recommended operating conditions. Exceeding this limit risks thermal overstress or long-term reliability degradation. For rheostat-mode use, ensure the applied voltage across RW–RL or RW–RH does not exceed 5mW power dissipation per DCP - corresponding to ≤22.4V across 50kΩ at full scale.
X95840UV20IZ-2.7T1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 4
- Number of Taps:
- 256
- Resistance (Ohms):
- 50k
- Interface:
- I2C
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 2.7V ~ 5.5V
- Features:
- Selectable Address
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±45ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-TSSOP
- Operating Temperature:
- -40°C ~ 85°C
- Resistance - Wiper (Ohms) (Typ):
- 70
X95840UV20IZ-2.7T1 FAQ
1.How can I place an order for X95840UV20IZ-2.7T1 through Aetrix?
Please submit a Request for Quotation (RFQ) for X95840UV20IZ-2.7T1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X95840UV20IZ-2.7T1 reliable?
The price and inventory of X95840UV20IZ-2.7T1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X95840UV20IZ-2.7T1 is usually 5 days.
3.What payment methods are accepted for X95840UV20IZ-2.7T1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X95840UV20IZ-2.7T1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X95840UV20IZ-2.7T1?
X95840UV20IZ-2.7T1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X95840UV20IZ-2.7T1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X95840UV20IZ-2.7T1?
For technical support, including X95840UV20IZ-2.7T1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X95840UV20IZ-2.7T1 requirements.
6.How does Aetrix verify that X95840UV20IZ-2.7T1 is sourced from the original manufacturer or authorized distributors?
All X95840UV20IZ-2.7T1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X95840UV20IZ-2.7T1 meets industry standards.
7.What is the process for return or replacement of X95840UV20IZ-2.7T1?
All X95840UV20IZ-2.7T1 units undergo pre-shipment inspection (PSI). If there is an issue with X95840UV20IZ-2.7T1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X95840UV20IZ-2.7T1 part is unused and in its original packaging.
Return procedure for X95840UV20IZ-2.7T1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
X95840UV20IZ-2.7T1 Tags

-
MCP4018T-103E/LT
Microchip Technology

-
MCP4018T-503E/LT
Microchip Technology

-
MCP4011T-103E/SN
Microchip Technology

-
MCP4018T-104E/LT
Microchip Technology

-
MCP4017T-503E/LT
Microchip Technology

-
MCP4018T-502E/LT
Microchip Technology

-
MCP4017T-103E/LT
Microchip Technology

-
MCP4531T-103E/MF
Microchip Technology

-
MCP4021T-202E/SN
Microchip Technology

-
MCP4023T-103E/CH
Microchip Technology

-
MCP4022T-503E/CH
Microchip Technology

-
MCP4551T-502E/MS
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

