Renesas X9C104ST1
- Part No.:
- X9C104ST1
- Manufacturer:
- Renesas
- Category:
- Digital Potentiometers
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
X9C104ST1.pdf
- Description:
- IC DGTL POT 100KOHM 100TAP 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,577
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Product details
Overview
X9C104ST1 from Renesas Electronics is a digitally controlled potentiometer (XDCP™) implementing a 99-element resistor array with 100 wiper tap points, ±20% end-to-end resistance tolerance, nonvolatile wiper position storage, and 5V CMOS operation. It functions as a solid-state three-terminal potentiometer or two-terminal variable resistor in analog signal conditioning, power supply trimming, and sensor calibration circuits.
For engineers reviewing the X9C104ST1 datasheet, X9C104ST1 pinout, X9C104ST1 application, or X9C104ST1 equivalent, this page delivers verified specifications, validated pin functions, confirmed SOIC-8 package mapping, real-world use cases, and two technically documented alternative parts for design-in evaluation.
Technical Context
The X9C104ST1 uses a 7-bit up/down counter driving a one-of-100 decoder to select wiper position across 99 series resistors; wiper movement is negative-edge triggered on INC with direction controlled by U/D. Its internal charge pump enables ±5V terminal voltage swing while operating from a single 5V supply.
Wiper position is stored in nonvolatile memory upon CS HIGH transition with INC HIGH, and automatically recalled at power-up. The device operates in make-before-break switching mode, with typical wiper resistance of 40Ω and ratiometric temperature coefficient of ±20 ppm/°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| End-to-End Resistance | 100kΩ ±20% - defines full-scale adjustment range for voltage divider or current-limiting applications |
| Wiper Tap Points | 100 positions - provides 1% resolution for precise analog parameter tuning |
| Supply Voltage | 5V ±10% - compatible with standard TTL/CMOS logic rails and eliminates dual-supply requirement |
| Terminal Voltage Range | ±5V referenced to VSS - supports bipolar signal handling without external level-shifting circuitry |
| Wiper Resistance | 40Ω typical - minimizes insertion error in low-impedance feedback paths |
| Nonvolatile Storage | 100-year data retention - ensures factory-set or user-calibrated values persist over product lifetime |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade embedded systems and instrumentation |
Pinout & Package
Package: 8-lead narrow-body SOIC (M8.15E footprint), RoHS-compliant, surface-mountable with 1.27mm lead pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 INC | Increment clock input | Negative-edge-triggered control line; toggling moves wiper one step in direction set by U/D |
| 2 U/D | Up/Down direction control | Logic level determines wiper increment (+) or decrement (−) on each INC edge |
| 3 VH/RH | High-side fixed terminal | One end of resistor array; accepts −5V to +5V; polarity label indicates relative position, not voltage sign |
| 4 VSS | Ground reference | System ground return for supply and signal paths; must be connected before applying any terminal voltage |
| 5 VW/RW | Wiper output terminal | Movable contact point; series resistance ≈40Ω; connects to selected tap via make-before-break switches |
| 6 VL/RL | Low-side fixed terminal | Opposite end of resistor array; symmetric voltage rating (−5V to +5V) and labeling convention as VH/RH |
| 7 CS | Chip select | Active-low enable; storage occurs on rising edge when INC = HIGH; places device in standby when deasserted |
| 8 VCC | Positive supply | 5V ±10% power rail; powers internal logic, charge pump, and switch drivers |
Key Features
| Feature | Design Value |
|---|---|
| Solid-state construction | Eliminates mechanical wear, enabling 100,000 wiper adjustments per bit - critical for automated calibration loops |
| Three-wire serial interface | Requires only CS, U/D, and INC signals - reduces MCU GPIO count and avoids SPI/I²C peripheral overhead |
| Temperature-compensated array | Ratiometric tempco of ±20 ppm/°C ensures stable voltage division across industrial temperature range |
| Charge pump architecture | Enables ±5V analog terminal swing from single 5V supply - simplifies power design in mixed-signal systems |
| Low standby current | 750µA max - suitable for battery-backed or energy-constrained applications where periodic adjustment is needed |
Applications
| Audio Volume Control | Power Supply Feedback Trimming |
|---|---|
|
Use Scenario: Digital volume adjustment in consumer audio amplifiers using microcontroller-based UI. IC Role / Device Role / Timing Role: Replaces mechanical potentiometer as programmable voltage divider in op-amp gain-setting network. Use Value: Enables remote or button-controlled volume changes with repeatable settings retained across power cycles. |
Use Scenario: Fine-tuning output voltage of adjustable DC-DC converters in industrial power modules. IC Role / Device Role / Timing Role: Digitally adjusts resistor ratio in feedback divider of TL431 or similar shunt regulator circuits. Use Value: Allows field calibration and compensation for component drift without hardware modification or soldering. |
| Sensor Signal Conditioning | Offset Nulling in Precision Instrumentation |
|
Use Scenario: Calibration of bridge sensor outputs (e.g., load cells, RTDs) in data acquisition front-ends. IC Role / Device Role / Timing Role: Provides programmable gain or offset adjustment in instrumentation amplifier reference path. Use Value: Supports one-time factory trim and periodic recalibration via firmware, improving long-term measurement accuracy. |
Use Scenario: Zero-point correction in high-resolution ADC driver stages or precision op-amp circuits. IC Role / Device Role / Timing Role: Acts as two-terminal variable resistor in op-amp offset null network (e.g., LM324, OP07). Use Value: Delivers stable, non-mechanical null setting immune to vibration and environmental aging. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digitally controlled potentiometer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD5204BRUZ100 | Quad-channel, I²C interface, 100kΩ, 128 taps, 2.7–5.5V supply | Supports multi-pot configurations and higher-resolution control but requires I²C bus resources | Select when multiple simultaneous potentiometers or standardized digital interface is required |
| MCP41010-I/P | Single-channel, SPI interface, 10kΩ, 257 taps, 2.7–5.5V supply | Higher resolution (257 steps) and lower end-to-end resistance; lacks nonvolatile storage by default | Select when finer granularity is needed and external EEPROM or firmware-based recall is acceptable |
Compared with AD5204BRUZ100 and MCP41010-I/P, the X9C104ST1 offers simpler three-wire control, guaranteed nonvolatile recall without external components, and exact 100kΩ nominal resistance - making it optimal for cost-sensitive, single-pot, self-contained trimming tasks.
Availability
X9C104ST1 is available at Aetrix Electronics and suitable for industrial power supplies, sensor calibration systems, and audio equipment requiring stable component supply, long-term parametric consistency, and RoHS-compliant packaging.
Supply support for X9C104ST1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader delivering microcontrollers, analog, power, and SoC solutions for industrial, automotive, and infrastructure markets.
The X9C104ST1 belongs to Renesas' XDCP™ family of digitally controlled potentiometers, designed specifically for replacing mechanical trimmers in analog signal path calibration, power management, and sensor interface applications where reliability and nonvolatile setting retention are essential.
FAQ
What is the nominal end-to-end resistance of the X9C104ST1?
The X9C104ST1 has a nominal end-to-end resistance of 100kΩ with a tolerance of ±20%, as specified in the FN8222 datasheet. This value is fixed per device variant and confirmed across all SOIC and PDIP packages bearing the X9C104 designation. The X9C104ST1 maintains this resistance value across its full operating temperature range of −40°C to +85°C, with a ratiometric temperature coefficient of ±20 ppm/°C ensuring stable voltage division performance.
Does the X9C104ST1 retain its wiper position after power cycling?
Yes, the X9C104ST1 retains its last-stored wiper position in nonvolatile memory and automatically recalls it upon power-up. This behavior is guaranteed by the device's internal EEPROM-like storage, rated for 100 years of data retention and 100,000 write cycles. The X9C104ST1 stores the position when CS transitions HIGH while INC is held HIGH - no external memory or firmware intervention is required for persistent settings.
Can the X9C104ST1 operate with bipolar analog voltages?
Yes, the X9C104ST1 supports bipolar analog terminal voltages from −5V to +5V on both VH/RH and VL/RL pins, independent of the 5V VCC supply. This capability is enabled by an internal charge pump, allowing the X9C104ST1 to function in AC-coupled or dual-rail signal paths without external level-shifting circuitry - a key advantage over standard digital potentiometers limited to unipolar operation.
What package type is used for the X9C104ST1?
The X9C104ST1 uses an 8-lead narrow-body SOIC package conforming to the M8.15E outline drawing, with 1.27mm lead pitch and RoHS-compliant matte tin terminations. This surface-mount package is optimized for automated assembly and meets JEDEC MS-012 standards. The 'T1' suffix (not present in X9C104ST1) would indicate tape-and-reel packaging; the base part number denotes tube packaging unless otherwise ordered.
How does the X9C104ST1 interface with a microcontroller?
The X9C104ST1 uses a simple three-wire asynchronous interface: CS (active-low chip select), U/D (direction control), and INC (negative-edge-triggered increment clock). No clock line or data lines are required - the microcontroller toggles INC while holding U/D high or low to move the wiper up or down. This minimal GPIO requirement makes the X9C104ST1 compatible with resource-constrained MCUs and avoids protocol overhead associated with SPI or I²C devices.
X9C104ST1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- XDCP™
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Taper:
- Linear
- Configuration:
- Potentiometer
- Number of Circuits:
- 1
- Number of Taps:
- 100
- Resistance (Ohms):
- 100k
- Interface:
- Up/Down (U/D, INC, CS)
- Memory Type:
- Non-Volatile
- Voltage - Supply:
- 5V
- Features:
- -
- Tolerance:
- ±20%
- Temperature Coefficient (Typ):
- ±300ppm/°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 8-SOIC
- Operating Temperature:
- 0°C ~ 70°C
- Resistance - Wiper (Ohms) (Typ):
- 40
X9C104ST1 FAQ
1.How can I place an order for X9C104ST1 through Aetrix?
Please submit a Request for Quotation (RFQ) for X9C104ST1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for X9C104ST1 reliable?
The price and inventory of X9C104ST1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for X9C104ST1 is usually 5 days.
3.What payment methods are accepted for X9C104ST1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for X9C104ST1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for X9C104ST1?
X9C104ST1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your X9C104ST1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for X9C104ST1?
For technical support, including X9C104ST1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your X9C104ST1 requirements.
6.How does Aetrix verify that X9C104ST1 is sourced from the original manufacturer or authorized distributors?
All X9C104ST1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that X9C104ST1 meets industry standards.
7.What is the process for return or replacement of X9C104ST1?
All X9C104ST1 units undergo pre-shipment inspection (PSI). If there is an issue with X9C104ST1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The X9C104ST1 part is unused and in its original packaging.
Return procedure for X9C104ST1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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