Texas Instruments XAM5728AABCXE
- Part No.:
- XAM5728AABCXE
- Manufacturer:
- Texas Instruments
- Category:
- Microprocessors
- Package:
- 760-BFBGA, FCBGA
- Datasheet:
-
XAM5728AABCXE.pdf
- Description:
- IC MPU SITARA 1.5GHZ 760FCBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
XAM5728AABCXE from Texas Instruments is a high-performance Sitara™ Arm® Cortex®-A15 applications processor with dual C66x DSPs, 2.5MB on-chip L3 RAM, dual DDR3/DDR3L memory interfaces supporting up to DDR3-1066, and integrated IVA-HD video subsystem enabling 4K@15fps H.264 encode/decode - deployed in industrial HMIs, automation gateways, and embedded vision edge nodes.
For engineers reviewing the XAM5728AABCXE datasheet, XAM5728AABCXE pinout, XAM5728AABCXE application, or XAM5728AABCXE equivalent, this page delivers verified silicon revision 2.0 specifications, validated 760-pin FCBGA package mapping, confirmed dual-Cortex-M4 co-processor support, PCIe Gen2 lane configuration options, and real-world use-case alignment for deterministic real-time control and analytics workloads.
Technical Context
The XAM5728AABCXE implements a heterogeneous multi-core architecture: two Arm Cortex-A15 CPUs handle OS-level tasks and application logic, while two TI C66x VLIW DSPs execute signal- and vision-intensive algorithms; both domains share coherent access to 2.5MB OCMC RAM with ECC and dual EMIF controllers driving up to 4GB total DDR3(L) memory.
Its programmable real-time layer includes two PRU-ICSS subsystems for industrial protocol offload (EtherCAT, Profinet), dual Cortex-M4 coprocessors (IPU1/IPU2) for low-latency image preprocessing, and four Embedded Vision Engines (EVEs) - though EVEs are disabled in XAM5728AABCXE per device comparison table - alongside hardware crypto accelerators (AES, SHA, RNG) and dual GMAC Ethernet with RGMII/MII/RMII support.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Dual Arm Cortex-A15 @ up to 1.5 GHz - enables Linux RT or Android with deterministic scheduling for HMI and gateway applications. |
| DSP Cores | Two C66x VLIW floating-point DSPs - object-code compatible with C64x+/C67x, delivering 32×16-bit fixed-point multiplies/cycle for radar or motor control math. |
| On-Chip RAM | 2.5MB OCMC RAM with ECC - provides low-latency, error-corrected scratchpad memory shared across MPU, DSP, GPU, and DMA engines. |
| Memory Interface | Dual DDR3/DDR3L EMIF - supports up to DDR3-1066 (533 MHz), 2GB per channel, enabling >8 GB/s aggregate bandwidth for video and analytics buffers. |
| Video Acceleration | IVA-HD subsystem - supports 4K@15fps H.264 encode/decode and 1080p60 for multiple codecs, used in digital signage and machine vision pre-processing. |
| Graphics | Dual-core PowerVR SGX544 3D GPU - renders OpenGL ES 2.0/3.0 graphics for rich GUIs in industrial HMIs without external GPU. |
| Connectivity | PCIe Gen2 (two 5-Gbps lanes), SATA Gen2, dual GMAC (RGMII/MII/RMII), USB 3.0 DRD + USB 2.0 DRD - enables high-speed peripheral expansion and storage interfacing. |
Pinout & Package
Package: 760-ball FCBGA (ABC), 23.0 mm × 23.0 mm, 0.8-mm pitch, RoHS-compliant. Ball grid conforms to TI's ABC package mechanical drawing and thermal pad layout per SPRS953G Rev G.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AB17 (rtc_porz) | RTC power-on reset input | Must tie to VSS when RTC unused; optional connection to PORZ with level translation if RTC enabled - affects warm-reset behavior. |
| AF14 (rtc_iso) | RTC isolation control | Pull to corresponding supply via external resistor if unused; connects to PORZ when RTC disabled - isolates RTC domain during deep-sleep modes. |
| K9 / Y14 / R20 / J16 | LD0 bypass capacitors | Capacitor terminals for vbbldo_dspeve, vbbldo_gpu, vbbldo_iva, vbbldo_mpu - require external 10–22 µF ceramic caps per LDO output. |
| L9 / J19 / Y15 / P19 / Y16 | DDR core voltage decoupling | Capacitor pads for vddram_core1–5 - placed adjacent to DDR BGA balls to minimize inductance in high-speed memory interface routing. |
| J10 / J9 / Y13 / T20 / K16 / K19 | DDR auxiliary voltage decoupling | Capacitor terminals for vddram_dspeve1/2, vddram_gpu, vddram_iva, vddram_mpu1/2 - critical for signal integrity on DDR clock and DQS strobes. |
| G19 | DCAN1 receive input | High-speed CAN 2.0B bus receiver - supports 1 Mbps operation; requires external termination and common-mode choke in automotive/industrial networks. |
Key Features
| Feature | Design Value |
|---|---|
| Dual Cortex-M4 coprocessors (IPU1/IPU2) | Offload real-time image scaling, sensor fusion, and protocol stack processing from A15 cores - reduces Linux kernel latency and improves determinism. |
| PRU-ICSS dual subsystems | Enable bit-banging of industrial protocols (e.g., EtherCAT, IO-Link) without CPU intervention - eliminates need for external ASICs or FPGAs in motion control systems. |
| VPE + Display subsystem | Hardware-accelerated video processing pipeline (deinterlacing, color space conversion) and triple-display controller (HDMI 1.4a + two LVDS/eDP outputs) - supports simultaneous 4K UI + dual 1080p video walls. |
| Crypto acceleration engine | Dedicated AES-128/256, SHA-1/256, DES/3DES, and TRNG blocks - accelerates secure boot, encrypted filesystems, and TLS handshake offload in edge gateways. |
| EDMA + System DMA | 32-channel enhanced DMA and system-level DMA controllers - enable zero-copy data movement between DDR, peripherals, and on-chip RAM for high-throughput sensor aggregation. |
Applications
| Industrial HMI Gateway | Machine Vision Edge Node |
|---|---|
|
Use Scenario: Multi-touch display with PLC integration, OPC UA server, and local analytics in factory-floor control panels. IC Role / Device Role / Timing Role: Central applications processor running Linux RT, managing GUI rendering, EtherCAT master stack, and time-synchronized sensor data ingestion. Use Value: Dual Cortex-A15 cores ensure responsive UI while C66x DSPs run FFT-based vibration analysis on accelerometer streams - all within single-chip thermal envelope. |
Use Scenario: Real-time defect detection on production line using 1080p camera input and neural network inference at <100ms latency. IC Role / Device Role / Timing Role: Vision accelerator host: IVA-HD handles H.264 decode and VPE performs color correction; EVEs are not enabled in XAM5728AABCXE, so CNN inference runs on C66x DSPs. Use Value: Hardware video decode + DSP-optimized OpenCL kernels deliver 12 FPS inference on ResNet-18 without external AI accelerator - reducing BOM cost and board area. |
| Energy Substation Controller | Smart Building Video Analytics Hub |
|
Use Scenario: IEC 61850-compliant protection relay with synchronized phasor measurement (PMU) and secure remote firmware updates. IC Role / Device Role / Timing Role: Time-critical control processor: PRU-ICSS executes GOOSE messaging and sample capture; crypto engine signs firmware images and validates certificates. Use Value: Sub-microsecond timestamping via PRU timers and hardware AES-256/SHA-256 enable compliance with IEC 62443-3-3 security requirements for critical infrastructure. |
Use Scenario: Occupancy analytics and people-counting across 4 HD cameras, with local storage via SATA SSD and cloud upload over dual-GMAC Ethernet. IC Role / Device Role / Timing Role: Multi-stream media hub: dual EMIFs feed DDR bandwidth to McASP audio, McSPI sensors, and eight McASP serializers for synchronized audio/video capture. Use Value: Eight McASP modules and quad SPI allow concurrent connection of microphones, environmental sensors, and eMMC boot storage - eliminating external I/O expanders. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar applications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM5729ABC | Includes four Embedded Vision Engines (EVEs); higher thermal design power (TDP) due to EVE activation; identical pinout and package. | Required for applications needing hardware-accelerated computer vision (e.g., stereo depth mapping, optical flow) beyond DSP-only compute. | Select AM5729ABC only if EVE-specific vision kernels are part of the software stack; otherwise XAM5728AABCXE offers identical CPU/DSP/GPU/peripheral capability at lower power. |
| AM5726ABC | Disables IVA-HD, HDMI, BB2D, SGX544 GPU, and VOUT1–3; retains dual A15, dual C66x, 2.5MB RAM, and full peripheral set except display/video blocks. | Suitable for headless control applications (e.g., PLC, RTU) where GUI/video is unnecessary; lower cost and reduced thermal load. | Choose AM5726ABC when display output, 3D graphics, or hardware video encode/decode are not required - saves ~$12/unit and simplifies thermal design. |
Compared with AM5729ABC, XAM5728AABCXE removes EVEs but retains full IVA-HD and GPU functionality, making it optimal for video-rich HMIs without vision acceleration; versus AM5726ABC, it adds HDMI, triple display pipelines, and SGX544 GPU - essential for graphical user interfaces and multimedia playback.
Availability
XAM5728AABCXE is available at Aetrix Electronics and suitable for industrial HMIs, automation gateways, and embedded vision edge nodes requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for safety-critical deployments.
Supply support for XAM5728AABCXE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, designing analog, embedded processing, and wireless chips for industrial, automotive, and communications markets since 1930.
The AM572x Sitara™ processor family targets high-performance embedded applications demanding heterogeneous compute, real-time I/O, and industrial-grade reliability - specifically engineered for HMIs, robotics, and intelligent edge analytics.
FAQ
What is the silicon revision of XAM5728AABCXE and why does it matter?
XAM5728AABCXE is silicon revision 2.0 per SPRS953G Rev G datasheet. This revision incorporates errata fixes for DDR timing, PRU-ICSS interrupt latency, and PCIe link training stability - critical for production designs requiring long-term reliability and compatibility with TI's Processor SDK 7.x+ toolchain.
Does XAM5728AABCXE support PCIe Gen3 or only Gen2?
XAM5728AABCXE supports PCIe Gen2 only - two 5-Gbps lanes configurable as one 2-lane port or two independent 1-lane ports. It does not implement Gen3 PHY or link layer; Gen3 capability is exclusive to AM574x and AM65x families per TI documentation.
Can XAM5728AABCXE run Linux with real-time patches, and what kernel version is validated?
Yes, XAM5728AABCXE is validated with Linux kernel 4.19 LTS and TI's PREEMPT_RT patchset in Processor SDK Linux 7.3+. The dual Cortex-A15 cores, GPMC, and PRU-ICSS enable sub-10µs interrupt latency for motion control and I/O synchronization in industrial Linux deployments.
What is the maximum DDR3 speed supported by XAM5728AABCXE, and how is bandwidth distributed?
XAM5728AABCXE supports DDR3-1066 (533 MHz) on both EMIF channels, delivering up to 8.5 GB/s aggregate bandwidth. Memory is interleaved across EMIF1 and EMIF2 in 256-byte chunks - enabling linear throughput scaling for video frame buffers and large analytics datasets in XAM5728AABCXE-based systems.
Is the HDMI interface on XAM5728AABCXE compliant with HDCP, and what resolution/timing modes are supported?
XAM5728AABCXE's HDMI encoder complies with HDMI 1.4a and DVI 1.0 standards but does not include HDCP encryption hardware. It supports resolutions up to 4K@30Hz (3840×2160) in YUV422 mode and Full HD 1920×1080@60Hz in RGB/YUV444 - validated in TI's AM5728 EVM reference design using XAM5728AABCXE silicon.
XAM5728AABCXE Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 760-BFBGA, FCBGA
- Series:
- Sitara™
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Core Processor:
- ARM® Cortex®-A15
- Number of Cores/Bus Width:
- 2 Core, 32-Bit
- Speed:
- 1.5GHz
- Co-Processors/DSP:
- DSP, BB2D, IPU, IVA, GPU, VPE
- RAM Controllers:
- DDR3, SRAM
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- -
- Ethernet:
- GbE
- SATA:
- SATA 3Gbps (1)
- USB:
- USB 2.0 (1), USB 3.0 (1)
- Voltage - I/O:
- 1.8V, 3.3V
- Operating Temperature:
- 0°C ~ 90°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 760-FCBGA (23x23)
- Additional Interfaces:
- CAN, EBI/EMI, HDQ/1-Wire®, I2C, McASP, McSPI, MMC/SD/SDIO, PCIe, QSPI, UART
XAM5728AABCXE FAQ
1.How can I place an order for XAM5728AABCXE through Aetrix?
Please submit a Request for Quotation (RFQ) for XAM5728AABCXE on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XAM5728AABCXE reliable?
The price and inventory of XAM5728AABCXE are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XAM5728AABCXE is usually 5 days.
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XAM5728AABCXE orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XAM5728AABCXE order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XAM5728AABCXE?
For technical support, including XAM5728AABCXE datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XAM5728AABCXE requirements.
6.How does Aetrix verify that XAM5728AABCXE is sourced from the original manufacturer or authorized distributors?
All XAM5728AABCXE products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XAM5728AABCXE meets industry standards.
7.What is the process for return or replacement of XAM5728AABCXE?
All XAM5728AABCXE units undergo pre-shipment inspection (PSI). If there is an issue with XAM5728AABCXE, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XAM5728AABCXE part is unused and in its original packaging.
Return procedure for XAM5728AABCXE:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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