AMD XC17128EPC20C

Overview

XC17128EPC20C from AMD is a 128K-bit serial configuration PROM designed for Xilinx FPGA configuration in industrial temperature grade (0°C to 70°C), featuring 5V supply voltage, 20-pin plastic DIP package, and 150 ns maximum access time. It stores bitstream data to initialize Spartan, Virtex, and XC4000-series FPGAs during power-up.

For engineers reviewing the XC17128EPC20C datasheet, pinout, applications, or equivalent options, key selection criteria include VCC compatibility with legacy 5V FPGA systems, DIP-20 through-hole mounting for prototyping and repair, and guaranteed 150 ns read timing under industrial temperature conditions.

Technical Context

This PROM operates in serial mode using a simple 2-wire interface (DATA and CONFIG) synchronized to an external clock signal, supporting master-mode configuration of Xilinx FPGAs. It requires no external address decoding logic and integrates internal address counters and output enable control.

The device uses NMOS technology with metal-gate transistors, enabling reliable operation at 5V with TTL-compatible input thresholds and open-drain DATA output. Its architecture supports single-cycle read access without wait states when interfaced with compatible FPGA configuration controllers.

Key Specifications

Pinout & Package

XC17128EPC20C is housed in a 20-pin plastic dual in-line package (PDIP) with 0.3-inch body width and 0.1-inch pin pitch, suitable for through-hole assembly and socket-based programming.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration PROM applications.

Compared with XC17128EPC20C, XCF01SVO20C enables higher-density configuration but mandates voltage and package redesign, while XC1764EPC20C offers pin-compatible cost savings at the expense of memory capacity-making XC17128EPC20C optimal for 128K-bit 5V industrial FPGA systems requiring DIP-20 fit.

Availability

XC17128EPC20C is available at Aetrix Electronics and suitable for FPGA configuration in industrial control panels, legacy system field repair, and prototyping platforms requiring stable component supply and long-term obsolescence management.

Supply support for XC17128EPC20C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

AMD acquired Xilinx in 2022 and now oversees legacy Xilinx programmable logic and configuration product lines, including PROMs, flash-based configuration devices, and related IP.

The XC17xx series was originally developed by Xilinx to provide standardized, low-risk configuration memory for its FPGA families, targeting reliability-critical industrial and communications applications.

FAQ

Is XC17128EPC20C compatible with Xilinx Spartan-3 FPGAs?

No, XC17128EPC20C is not compatible with Spartan-3 FPGAs. Spartan-3 requires 3.3V or 1.2V configuration interfaces and supports only XCFxx platform flash devices or JTAG-based configuration. XC17128EPC20C is specified for 5V operation and targets XC4000, Spartan-XL, and early Virtex families. Using XC17128EPC20C with Spartan-3 would violate voltage and protocol requirements.

What is the maximum clock frequency supported by XC17128EPC20C during configuration?

XC17128EPC20C does not specify a maximum clock frequency; instead, it guarantees a minimum pulse width of 100 ns for the CONFIG signal and a maximum access time of 150 ns. This allows reliable operation with CONFIG clock periods ≥300 ns (i.e., ≤3.3 MHz), consistent with Xilinx XC4000-series FPGA configuration controllers.

Can XC17128EPC20C be programmed in-system using standard tools?

No, XC17128EPC20C is OTP (one-time programmable) and requires external PROM programmers such as the Xilinx Parallel Cable III or third-party universal programmers with NMOS PROM algorithms. It cannot be reprogrammed in-system or via JTAG, and no in-field update capability exists after initial programming.

Does XC17128EPC20C support daisy-chain configuration with multiple devices?

No, XC17128EPC20C does not support daisy-chaining. It uses a dedicated 2-wire serial interface (CONFIG/DATA) intended for point-to-point FPGA configuration. Multi-device configurations require separate CONFIG signals or external multiplexing logic-not inherent to XC17128EPC20C functionality.

What is the data retention specification for XC17128EPC20C?

XC17128EPC20C guarantees 20 years of data retention at 25°C ambient temperature, per Xilinx specification DS029. Retention decreases with elevated operating temperature; at maximum industrial temperature (70°C), expected retention remains above 10 years under normal operating conditions.