AMD XC17128EPD8C
- Part No.:
- XC17128EPD8C
- Manufacturer:
- AMD
- Category:
- Configuration PROMs for FPGAs
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
XC17128EPD8C.pdf
- Description:
- IC PROM SERIAL CONFIG 128K 8-DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
XC17128EPD8C from AMD is a 128K-bit serial PROM configured for Xilinx FPGA configuration, operating at 5V supply voltage with 150 ns access time and industrial temperature range (–40°C to +85°C), used in embedded reconfiguration of Spartan and Virtex family FPGAs.
For engineers reviewing the XC17128EPD8C datasheet, pinout, applications, or equivalent options, key selection criteria include VCC compatibility, read access timing, serial interface protocol, and JEDEC-standard SOIC-8 package footprint.
Technical Context
This device implements a synchronous serial interface compliant with Xilinx configuration protocol, supporting master serial mode for FPGA bitstream loading. It uses NMOS technology with TTL-compatible inputs and outputs, and includes internal address counter for sequential read operation.
XC17128EPD8C features no internal write logic - it is factory-programmed and read-only. Data retention exceeds 20 years at 85°C, and it supports single-supply 5V operation without external level-shifting circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16 K × 8) - provides full configuration bitstream storage for mid-complexity Xilinx FPGAs like XC4000E/XC4000X series. |
| Supply Voltage | 5.0 V ±10% - compatible with legacy 5V FPGA configuration power rails and eliminates need for voltage translators. |
| Access Time | 150 ns max - ensures reliable timing margin for FPGA configuration clock rates up to 6.67 MHz. |
| Operating Temp | –40°C to +85°C - qualified for industrial-grade embedded systems requiring extended thermal stability. |
| Package | SOIC-8 (300 mil) - JEDEC MS-012 standard footprint, compatible with automated PCB assembly and legacy board layouts. |
| Interface | Serial synchronous (CLK/DATA) - matches Xilinx Master Serial configuration mode, requiring only two FPGA I/O pins. |
Pinout & Package
XC17128EPD8C is housed in an 8-pin plastic small-outline integrated circuit (SOIC-8) package with 300-mil body width and standard gull-wing lead form.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Address Input | Not connected internally; pin is no-connect per datasheet - must be left unconnected or tied to GND. |
| CLK | Serial Clock Input | Edge-triggered input synchronizing data output; driven by FPGA configuration controller. |
| DOUT | Data Output | CMOS-level serial data stream delivering configuration bits LSB-first to FPGA DIN pin. |
| VCC | Power Supply | +5V supply pin; requires local 0.1 µF ceramic decoupling capacitor near the package. |
| GND | Ground Reference | System ground return path; must be low-impedance connection shared with FPGA configuration circuitry. |
| CE | Chip Enable Input | Active-low enable; held low during configuration; high state disables output and reduces standby current. |
| OE | Output Enable Input | Active-low control; must be low to enable DOUT driver; tied low permanently in most designs. |
| NC | No Connect | Pin 1 is not bonded; must remain unconnected - no pull-up/down or routing required. |
Key Features
| Feature | Design Value |
|---|---|
| Factory-programmed memory | Eliminates field programming risk and ensures bitstream integrity across production batches. |
| TTL-compatible I/O | Direct interface with 5V FPGA configuration pins without level-shifting components or design overhead. |
| Single 5V supply | Reduces BOM count and simplifies power architecture versus multi-voltage PROM solutions. |
| Industrial temperature rating | Enables deployment in harsh environments such as factory automation controllers and outdoor telecom equipment. |
| JEDEC SOIC-8 footprint | Supports drop-in replacement of legacy configuration PROMs and leverages existing PCB tooling and assembly processes. |
Applications
| Industrial PLC Configuration | Telecom Line Card Boot |
|---|---|
Use Scenario: Reconfiguring Xilinx Spartan-II FPGAs in programmable logic controllers during firmware updates or field maintenance. IC Role / Device Role / Timing Role: Serial configuration PROM providing deterministic bitstream load sequence synchronized to FPGA's CCLK signal. Use Value: Ensures repeatable, glitch-free FPGA initialization under variable ambient temperatures and EMI conditions. | Use Scenario: Storing and delivering boot configuration data to Xilinx Virtex-E FPGAs on carrier-grade line interface cards. IC Role / Device Role / Timing Role: Nonvolatile configuration source enabling hot-swap-capable FPGA reload without system reset. Use Value: Maintains operational continuity during service module replacement while meeting Telcordia GR-1089 immunity requirements. |
| Medical Imaging Subsystem | Avionics Test Equipment |
Use Scenario: Loading diagnostic FPGA configurations in portable ultrasound processors where reliability and long-term data retention are critical. IC Role / Device Role / Timing Role: Read-only memory holding validated bitstreams for real-time image processing pipelines. Use Value: Guarantees bitstream authenticity over 10+ years of field use without battery-backed retention mechanisms. | Use Scenario: Configuring Xilinx XC4062XV FPGAs in ATE platforms performing DO-254-compliant functional testing of flight control modules. IC Role / Device Role / Timing Role: Certified configuration memory supporting traceable, auditable FPGA startup sequences. Use Value: Meets RTCA/DO-254 hardware lifecycle documentation requirements for airborne electronic hardware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration PROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| XCF01SVO20C | 1 Mbit capacity, 3.3V supply, VQFP-20 package - higher density but incompatible voltage and footprint. | Targets newer 3.3V Xilinx FPGAs (Spartan-3, Virtex-II); not suitable for legacy 5V systems. | Select only when migrating to 3.3V FPGA families and redesigning PCB layout. |
| AT17LV010-10PU | 1 Mbit, 3.3V/2.5V dual-supply, PDIP-20 package - wider voltage range but larger package and different pinout. | Used in mixed-voltage prototyping boards; lacks industrial temp rating and SOIC-8 compatibility. | Prefer for lab validation; avoid for volume industrial deployments requiring SOIC-8 footprint and –40°C operation. |
Compared with XCF01SVO20C and AT17LV010-10PU, XC17128EPD8C offers guaranteed 5V operation, SOIC-8 mechanical compatibility, and industrial temperature support - making it the only option for maintaining legacy FPGA configuration infrastructure without PCB revision.
Availability
XC17128EPD8C is available at Aetrix Electronics and suitable for industrial PLCs, telecom line cards, and medical imaging subsystems requiring stable component supply and long-lifecycle support.
Supply support for XC17128EPD8C includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
AMD (acquired Xilinx in 2022) is a global semiconductor leader specializing in adaptive computing, FPGA, and programmable logic technologies.
The XC17xxx series was originally developed by Xilinx to provide standardized, factory-programmed configuration memory for early-generation SRAM-based FPGAs, targeting cost-sensitive, high-reliability embedded systems.
FAQ
Is XC17128EPD8C still in production or considered obsolete?
XC17128EPD8C is listed as active and available through authorized distributors and Aetrix Electronics. While newer FPGA families use different configuration schemes, this part remains supported for legacy system maintenance and repair. No obsolescence notice has been issued by AMD/Xilinx for XC17128EPD8C.
Can XC17128EPD8C be reprogrammed in-system?
No, XC17128EPD8C is a one-time-programmable (OTP) PROM manufactured with factory-programmed data. It contains no internal write circuitry or erase capability. Reprogramming requires physical replacement with a newly programmed unit. XC17128EPD8C is strictly read-only during operation.
What FPGA families are explicitly supported by XC17128EPD8C?
XC17128EPD8C is documented for use with Xilinx XC4000E, XC4000EX, XC4000XL, and Spartan-XL FPGA families. Its timing and interface match the Master Serial configuration mode specified in Xilinx Application Note XAPP058 for those devices.
Does XC17128EPD8C require external pull-up resistors on any pins?
No external pull-ups are required. CE and OE are active-low inputs and must be held low during configuration; they are typically hard-wired to GND. CLK and DOUT have no pull requirements per the datasheet. XC17128EPD8C drives all outputs actively and does not rely on external termination.
How is data integrity verified during XC17128EPD8C read operations?
Data integrity relies on manufacturing test and long-term retention qualification - XC17128EPD8C has no built-in CRC, parity, or error-checking circuitry. Verification occurs externally via FPGA configuration controller logic that monitors INIT_B and DONE signals and retries on failure. XC17128EPD8C itself performs no internal validation.
XC17128EPD8C Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- OTP
- Memory Size:
- 128kb
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
XC17128EPD8C FAQ
1.How can I place an order for XC17128EPD8C through Aetrix?
Please submit a Request for Quotation (RFQ) for XC17128EPD8C on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XC17128EPD8C reliable?
The price and inventory of XC17128EPD8C are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XC17128EPD8C is usually 5 days.
3.What payment methods are accepted for XC17128EPD8C?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XC17128EPD8C transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XC17128EPD8C?
XC17128EPD8C orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XC17128EPD8C order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XC17128EPD8C?
For technical support, including XC17128EPD8C datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XC17128EPD8C requirements.
6.How does Aetrix verify that XC17128EPD8C is sourced from the original manufacturer or authorized distributors?
All XC17128EPD8C products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XC17128EPD8C meets industry standards.
7.What is the process for return or replacement of XC17128EPD8C?
All XC17128EPD8C units undergo pre-shipment inspection (PSI). If there is an issue with XC17128EPD8C, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XC17128EPD8C part is unused and in its original packaging.
Return procedure for XC17128EPD8C:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
XC17128EPD8C Tags

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AT17LV512A-10PU
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EPCQ4ASI8N
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EPCQ32ASI8N
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EPCQ64ASI16N
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EPCQ128ASI16N
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AT17LV512A-10JU
Microchip Technology

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AT17LV512-10JU
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AT17LV010-10JU
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