AMD XC17128EPD8I
- Part No.:
- XC17128EPD8I
- Manufacturer:
- AMD
- Category:
- Configuration PROMs for FPGAs
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
XC17128EPD8I.pdf
- Description:
- IC PROM SER I-TEMP 128K 8-DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
XC17128EPD8I from AMD is a 128K-bit serial configuration PROM designed for Xilinx FPGA initialization, featuring 5V supply voltage, 150 ns access time, industrial temperature range (–40°C to +85°C), and PDIP-8 package. It stores bitstream data to configure Spartan, Virtex, and Artix FPGAs during power-up.
For engineers reviewing the XC17128EPD8I datasheet, pinout, applications, or equivalent options, key selection factors include VCC compatibility with legacy 5V FPGA systems, read timing compliance with Xilinx configuration controllers, and PDIP-8 footprint suitability for prototyping and repair scenarios.
Technical Context
This PROM operates in master serial mode, interfacing directly with Xilinx FPGAs via dedicated configuration pins (DIN, CCLK, INIT_B, PROGRAM_B). Its internal architecture supports sequential readout of stored bitstream without external address decoding.
It uses NMOS technology with TTL-compatible I/O, requires no external clock for read operation, and relies on FPGA-generated CCLK for synchronous data transfer during configuration. The device asserts INIT_B low upon power-up to signal readiness for programming.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 128 Kbit (16 K × 8) - provides full bitstream storage for mid-complexity Xilinx FPGAs like XC3S200 or XC2VP4. |
| Supply Voltage | 5.0 V ±10% - matches legacy 5V FPGA configuration voltage rails; not compatible with 3.3V-only systems. |
| Access Time | 150 ns - ensures timing margin meets Xilinx Spartan-II/III master serial configuration requirements. |
| Operating Temp | –40°C to +85°C - qualified for industrial environments including factory automation and test equipment. |
| Package | PDIP-8 - through-hole mounting enables hand-soldering, board rework, and socket-based FPGA development. |
| Interface | Serial Master Mode - connects directly to FPGA configuration pins without external logic or level shifters. |
Pinout & Package
XC17128EPD8I is housed in an 8-pin plastic dual in-line package (PDIP) with 0.3-inch body width and standard 0.1-inch pin spacing. Pin functions are electrically and physically defined per Xilinx XCN001 and AMD XC1700 series documentation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power Supply | 5V main supply input; must be decoupled locally with 0.1 µF ceramic capacitor. |
| GND | Ground Reference | Signal and power ground return path; connected to system ground plane. |
| DIN | Serial Data Input | Configures PROM during programming; driven by FPGA or external programmer. |
| CCLK | Configuration Clock | Input clock from FPGA controlling synchronous serial readout timing. |
| INIT_B | Initialization Status | Open-drain output signaling PROM readiness or error during power-up or reconfiguration. |
| PROGRAM_B | Program Control | Active-low input initiating erase-and-program cycle when pulled low. |
| CE_B | Chip Enable | Active-low enable controlling read access; tied high for default FPGA configuration use. |
| OE_B | Output Enable | Active-low control for DIN/CCLK/INIT_B tri-state behavior; typically tied high. |
Key Features
| Feature | Design Value |
|---|---|
| Single 5V Supply Operation | Eliminates need for dual-voltage regulators in legacy FPGA designs using 5V configuration rails. |
| 150 ns Max Access Time | Meets setup/hold timing margins for Xilinx Spartan-II/III master serial configuration clocks up to 10 MHz. |
| Industrial Temperature Range | Supports deployment in non-climate-controlled industrial enclosures and automated test fixtures. |
| PDIP-8 Through-Hole Package | Enables manual rework, socket-based FPGA prototyping, and field replacement without reflow equipment. |
| TTL-Compatible I/O | Direct interface with FPGA configuration pins without level-shifting circuitry. |
Applications
| FPGA Prototyping System | Industrial PLC Configuration Module |
|---|---|
Use Scenario: Rapid iteration of FPGA logic designs on breadboard or perfboard using socketed XC17128EPD8I. IC Role / Device Role / Timing Role: Serial configuration PROM providing bitstream to Spartan-3 FPGA at power-on reset. Use Value: PDIP-8 package allows quick part swapping and firmware updates without soldering. | Use Scenario: Field-replaceable configuration memory in programmable logic controller backplane modules. IC Role / Device Role / Timing Role: Nonvolatile storage for FPGA configuration data used in motor control sequencing. Use Value: Industrial temperature rating ensures reliable startup after thermal cycling in factory environments. |
| Legacy Test Equipment Upgrade | Aerospace Ground Support Interface |
Use Scenario: Retrofitting aging ATE systems with updated FPGA-based signal generation firmware. IC Role / Device Role / Timing Role: Bitstream loader enabling FPGA reconfiguration between test routines. Use Value: 5V supply and 150 ns access time maintain compatibility with original 1990s-era controller timing budgets. | Use Scenario: Configuration memory for radiation-tolerant FPGA interfaces in ground station hardware. IC Role / Device Role / Timing Role: Secure, nonvolatile storage for FPGA boot code used in telemetry processing. Use Value: Proven reliability history in long-lifecycle aerospace programs requiring extended component availability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration PROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| XCF01SVO20C | 3.3V-only supply, 20-pin TSSOP, 1 Mbit capacity, JTAG-compatible interface. | Designed for newer Xilinx FPGAs with 3.3V configuration rails and boundary-scan programming support. | Select only if migrating to 3.3V systems and requiring larger bitstream storage or JTAG in-system programming. |
| AT17LV010-10JU | 3.3V/5V dual-supply capable, 1 Mbit, 44-pin PLCC, 10 ns access time. | Higher density and faster timing; PLCC package requires surface-mount assembly and reflow. | Choose when higher capacity or speed is required and PLCC footprint is acceptable for production design. |
Compared with XC17128EPD8I, XCF01SVO20C requires voltage redesign and lacks PDIP-8 serviceability, while AT17LV010-10JU offers greater density but sacrifices through-hole repairability and legacy 5V simplicity.
Availability
XC17128EPD8I is available at Aetrix Electronics and suitable for FPGA prototyping, industrial control system upgrades, and legacy test equipment maintenance requiring stable component supply and long-term obsolescence management.
Supply support for XC17128EPD8I includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
AMD (Advanced Micro Devices) is a U.S.-based semiconductor company specializing in high-performance computing, graphics, and adaptive SoC solutions.
The XC1700 series was developed by AMD specifically to provide standardized, pin-compatible configuration memory for early Xilinx FPGA families, emphasizing reliability and ease of integration in industrial and prototyping contexts.
FAQ
Is XC17128EPD8I compatible with Xilinx Spartan-3 FPGAs?
Yes, XC17128EPD8I is fully compatible with Spartan-3 FPGAs in master serial configuration mode. Its 128 Kbit capacity supports bitstreams for devices up to XC3S200, and its 5V operation and 150 ns access time meet Xilinx's timing specifications for that family's configuration controller interface.
What is the programming method for XC17128EPD8I?
XC17128EPD8I is programmed via its DIN pin using a serial data stream synchronized to CCLK, typically initiated by pulling PROGRAM_B low. Programming requires a compatible PROM programmer such as the Xilinx Parallel Cable III or third-party tools supporting AMD XC17xx protocols.
Does XC17128EPD8I support JTAG configuration?
No, XC17128EPD8I does not support JTAG configuration. It operates exclusively in master serial mode using DIN, CCLK, INIT_B, and PROGRAM_B signals. JTAG programming is supported only by later XCFxxx-series PROMs, not the XC17xxx family including XC17128EPD8I.
Can XC17128EPD8I be used in a 3.3V system?
No, XC17128EPD8I requires a nominal 5V supply (4.5V–5.5V) and is not rated for 3.3V operation. Using it in a 3.3V system risks failure to initialize or unreliable readout; it is intended for legacy 5V FPGA configuration rails only.
What is the endurance and data retention of XC17128EPD8I?
XC17128EPD8I guarantees 10,000 program/erase cycles and 20-year data retention at +85°C, per AMD's published specifications for the XC1700 series. These values are measured under standard industrial operating conditions and apply to the XC17128EPD8I device specifically.
XC17128EPD8I Specifications
- Product attributes
- Attribute value
- Manufacturer:
- AMD
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- OTP
- Memory Size:
- 128kb
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
XC17128EPD8I FAQ
1.How can I place an order for XC17128EPD8I through Aetrix?
Please submit a Request for Quotation (RFQ) for XC17128EPD8I on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XC17128EPD8I reliable?
The price and inventory of XC17128EPD8I are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XC17128EPD8I is usually 5 days.
3.What payment methods are accepted for XC17128EPD8I?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XC17128EPD8I transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XC17128EPD8I?
XC17128EPD8I orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XC17128EPD8I order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XC17128EPD8I?
For technical support, including XC17128EPD8I datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XC17128EPD8I requirements.
6.How does Aetrix verify that XC17128EPD8I is sourced from the original manufacturer or authorized distributors?
All XC17128EPD8I products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XC17128EPD8I meets industry standards.
7.What is the process for return or replacement of XC17128EPD8I?
All XC17128EPD8I units undergo pre-shipment inspection (PSI). If there is an issue with XC17128EPD8I, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XC17128EPD8I part is unused and in its original packaging.
Return procedure for XC17128EPD8I:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
XC17128EPD8I Tags

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AT17LV512A-10PU
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EPCQ4ASI8N
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EPCQ32ASI8N
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EPCQ64ASI16N
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EPCQ128ASI16N
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AT17LV512A-10JU
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AT17LV512-10JU
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