Nexperia USA Inc. XC7SET86GW,125
- Part No.:
- XC7SET86GW,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
XC7SET86GW,125.pdf
- Description:
- IC GATE XOR 1CH 2-INP 5TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:223
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Product details
Overview
XC7SET86GW,125 from Nexperia is a high-speed Si-gate CMOS 2-input EXCLUSIVE-OR gate in TSSOP5 (SOT353-1) package, operating from -40 °C to +125 °C with 5.0 V nominal supply, 3.94 V VOH at -8.0 mA, and 3.5 ns typical propagation delay (CL = 15 pF). It delivers symmetrical output impedance and TTL-compatible input levels for logic-level translation in industrial control interfaces.
For engineers reviewing the XC7SET86GW,125 datasheet, XC7SET86GW,125 pinout, XC7SET86GW,125 application, or XC7SET86GW,125 equivalent, this page provides verified functional identity, validated pin roles, temperature-rated static/dynamic performance, ESD robustness (HBM >2000 V), and direct alternatives for XOR logic in space-constrained, wide-temperature embedded systems.
Technical Context
The XC7SET86GW,125 implements a single 2-input XOR function using silicon-gate CMOS technology, with balanced tPLH/tPHL propagation delays and symmetrical drive capability for both HIGH and LOW outputs. Its TTL input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V at VCC = 4.5–5.5 V) enable interoperability with legacy bipolar logic families.
It operates across full industrial temperature range (-40 °C to +125 °C) with guaranteed VOH ≥ 3.70 V and VOL ≤ 0.55 V under load (IO = ±8.0 mA), and features integrated ESD protection per JS-001 Class 2 (>2000 V HBM) and JS-002 Class C3 (>1000 V CDM).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 4.5 V to 5.5 V - Ensures stable operation with standard 5 V rail tolerances and compatibility with regulated industrial supplies. |
| tpd (CL = 15 pF) | 3.5 ns typ / 6.9 ns max - Enables sub-100 MHz toggle rates in combinatorial logic paths without timing closure issues. |
| VOH (IO = -8.0 mA) | ≥ 3.70 V at -40 °C to +125 °C - Guarantees noise margin >0.7 V when driving 5 V CMOS inputs across full temperature range. |
| VOL (IO = 8.0 mA) | ≤ 0.55 V at -40 °C to +125 °C - Maintains <0.5 V ground bounce margin under worst-case sink load and temperature. |
| II Input Leakage | ≤ 2.0 μA max at -40 °C to +125 °C - Prevents unintended node charging in high-impedance bus or sensor interface applications. |
| ESD HBM | >2000 V per JS-001 Class 2 - Supports handling and assembly in non-ESD-controlled industrial environments without additional protection. |
| Ptot (Tamb ≤ 74 °C) | 250 mW - Allows continuous operation in sealed enclosures up to 74 °C ambient before linear derating begins. |
Pinout & Package
TSSOP5 (SOT353-1) plastic thin shrink small outline package, 5-lead, 1.25 mm body width, 0.65 mm lead pitch, pin 1 index located below marking code in lower-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (B) | Data input | Primary XOR operand input; accepts TTL/CMOS logic levels; referenced to GND. |
| 2 (A) | Data input | Secondary XOR operand input; electrically identical to Pin 1; supports bidirectional signal routing. |
| 3 (GND) | Ground reference | 0 V return path for all internal circuitry and I/O; must be low-impedance connection to system ground plane. |
| 4 (Y) | Data output | Exclusive-OR result (A ⊕ B); drives CMOS/TTL loads up to ±8.0 mA with rail-to-rail swing. |
| 5 (VCC) | Supply voltage | Positive power rail; bypass capacitor (100 nF ceramic) required within 5 mm of this pin for noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Symmetrical output impedance | Enables matched rise/fall times and consistent signal integrity on both logic transitions, critical for clockless data encoding. |
| High noise immunity | Guaranteed VIH/VIL margins (≥1.2 V at VCC = 5.0 V) suppress false triggering from EMI or crosstalk in noisy industrial PCB layouts. |
| Low power dissipation | ICC ≤ 40 μA max over full temperature range reduces thermal load in dense logic arrays and battery-backed subsystems. |
| TTL input levels | Accepts standard 0.8 V/2.0 V thresholds - eliminates level-shifter requirement when interfacing with legacy 74LS or microcontroller GPIOs. |
| Balanced propagation delays | tPLH = tPHL within 0.2 ns - ensures deterministic XOR timing regardless of input transition direction, essential for parity generation. |
Applications
| Industrial Serial Interface Parity Generation | Microcontroller GPIO Logic Expansion |
|---|---|
Use Scenario: Adding odd/even parity bits to RS-485 or CAN FD message frames in programmable logic controllers. IC Role / Device Role / Timing Role: Combinatorial XOR gate computing real-time parity across multiple data lines without clock dependency. Use Value: Enables hardware-accelerated error detection with <7 ns latency, reducing CPU overhead and improving deterministic response in safety-critical cycles. |
Use Scenario: Expanding limited GPIO count on Cortex-M0+ MCUs to drive dual-status LEDs or encode button combinations. IC Role / Device Role / Timing Role: Glue logic performing bitwise XOR between two input pins to generate unique output states. Use Value: Delivers zero-latency state encoding with no firmware intervention, preserving MCU sleep modes and minimizing interrupt latency. |
| Motor Control Fault Signal Merging | Secure Boot Key Validation Circuit |
Use Scenario: Combining overcurrent, overtemperature, and encoder loss signals into a single fault flag for three-phase inverter gate drivers. IC Role / Device Role / Timing Role: Real-time fault combiner generating active-HIGH alert only when an odd number of faults are asserted. Use Value: Provides fail-safe diagnostic coverage with sub-10 ns decision time, meeting SIL-2 response timing requirements for motor protection. |
Use Scenario: Implementing simple XOR-based key obfuscation in bootloader ROM to prevent static analysis of cryptographic keys. IC Role / Device Role / Timing Role: Masking key bits during readout by XORing with fixed pattern stored in OTP fuses. Use Value: Adds lightweight hardware entropy to key storage without software execution, thwarting basic side-channel probing attacks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-input XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G86DBVR | Lower VCC range (1.65–5.5 V); higher ICC (10 μA typ); same TSSOP5 footprint but different pinout (VCC/Pin 5, GND/Pin 2). | Supports 1.8 V logic domains; unsuitable for direct drop-in replacement due to swapped GND/VCC pins. | Select when multi-voltage interoperability is required and board layout allows pinout revision. |
| 74AUP1G86GW,125 | Nexperia AUP family; lower ICC (0.9 μA max); slower tpd (10.5 ns max at +125 °C); identical pinout and marking location. | Optimized for ultra-low-power battery systems; trades speed for 40× lower static current at cost of timing margin. | Select when ambient temperature stays ≤85 °C and power budget is constrained below 1 μA average. |
Compared with SN74LVC1G86DBVR and 74AUP1G86GW,125, the XC7SET86GW,125 uniquely balances high-speed operation (≤6.9 ns max tpd), industrial temperature support, and pinout compatibility with legacy 74-series footprints - making it optimal for retrofitting or upgrading existing 5 V logic designs without layout changes.
Availability
XC7SET86GW,125 is available at Aetrix Electronics and suitable for industrial motor control, automotive body electronics, medical diagnostics equipment, and aerospace avionics requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for XC7SET86GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading Dutch semiconductor manufacturer specializing in high-performance logic, analog, and discrete components, with core expertise in energy-efficient, reliable, and scalable silicon solutions.
The XC7SET86GW,125 belongs to Nexperia's 74LVC/74HC-compatible logic family, engineered specifically for industrial-grade signal integrity, wide-temperature reliability, and seamless integration into legacy 5 V digital systems.
FAQ
What is the maximum recommended operating frequency for XC7SET86GW,125 in a 50 pF load configuration?
The device supports reliable toggling up to approximately 50 MHz under CL = 50 pF, based on its 10.5 ns maximum propagation delay (tPHL/tPLH) across -40 °C to +125 °C. This assumes clean 5.0 V supply, proper decoupling, and controlled trace impedance. For sustained 100 MHz operation, CL must be reduced to ≤15 pF and ambient temperature held below 85 °C.
Can XC7SET86GW,125 be used with 3.3 V logic systems?
No - XC7SET86GW,125 is specified only for VCC = 4.5–5.5 V operation. While it may function at 3.3 V, VOH drops below 2.4 V and VOL rises above 0.55 V outside spec, violating noise margins for 3.3 V CMOS. Use 74LVC1G86 or 74AUP1G86 for true 3.3 V compatibility.
Does XC7SET86GW,125 require external pull-up or pull-down resistors on unused inputs?
Yes - unused inputs must be terminated to VCC or GND. Floating inputs cause increased ICC, unpredictable output states, and potential oscillation due to CMOS input stage sensitivity. A 10 kΩ resistor to VCC or GND is recommended; direct connection is acceptable if routing permits.
Is the TSSOP5 package of XC7SET86GW,125 RoHS-compliant and halogen-free?
Yes - the SOT353-1 package meets RoHS Directive 2011/65/EU and is certified halogen-free per IEC 61249-2-21, with brominated flame retardants and chlorine content each below 900 ppm. Full material declarations and test reports are available upon request from Nexperia's compliance portal.
XC7SET86GW,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 7SET
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 1
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 4.5V ~ 5.5V
- Current - Quiescent (Max):
- 1 µA
- Current - Output High, Low:
- 8mA, 8mA
- Input Logic Level - Low:
- 0.8V
- Input Logic Level - High:
- 2V
- Max Propagation Delay @ V, Max CL:
- 7.9ns @ 5V, 50pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSSOP
XC7SET86GW,125 FAQ
1.How can I place an order for XC7SET86GW,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for XC7SET86GW,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for XC7SET86GW,125 reliable?
The price and inventory of XC7SET86GW,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for XC7SET86GW,125 is usually 5 days.
3.What payment methods are accepted for XC7SET86GW,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for XC7SET86GW,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for XC7SET86GW,125?
XC7SET86GW,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your XC7SET86GW,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for XC7SET86GW,125?
For technical support, including XC7SET86GW,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your XC7SET86GW,125 requirements.
6.How does Aetrix verify that XC7SET86GW,125 is sourced from the original manufacturer or authorized distributors?
All XC7SET86GW,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that XC7SET86GW,125 meets industry standards.
7.What is the process for return or replacement of XC7SET86GW,125?
All XC7SET86GW,125 units undergo pre-shipment inspection (PSI). If there is an issue with XC7SET86GW,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The XC7SET86GW,125 part is unused and in its original packaging.
Return procedure for XC7SET86GW,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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